KR0172782B1 - Method for forming contact of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact of a semiconductor device and a method of manufacturing the same, wherein a polysilicon layer pattern stacked on top of a gate electrode is thermally oxidized after a contact etching process for use as an etch barrier in forming a self-aligned contact. Since a short circuit is prevented and a short circuit between adjacent contacts is also prevented, process yield and reliability of device operation can be improved.

Description

Contact of semiconductor device and manufacturing method thereof

1 is a cross-sectional view of a semiconductor device in which a contact according to the prior art is formed.

2 is a cross-sectional view of a semiconductor device in which a contact is formed according to the first embodiment of the present invention.

3A to 3E are views of a process for manufacturing a contact of a semiconductor device according to the first embodiment of the present invention.

4 is a cross-sectional view of a semiconductor device in which a contact is formed in accordance with a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 well region

3: device isolation oxide film 4: gate oxide film

5 gate electrode 6 first insulating film

7: polycrystalline silicon 8: nitride film spacer

9 source / drain electrode 10 interlayer insulating film

11: upper conductive wiring 15: contact hole

20: thermal oxide film 25: oxide film spacer

The present invention relates to a semiconductor device and a method of manufacturing the same, in particular, by thermally oxidizing the exposed portion through the contact hole of the polysilicon layer pattern used as an etch barrier when forming the contact hole to prevent short-term occurrence of short-circuit with adjacent contact holes A semiconductor device capable of improving process yield and reliability of device operation, and a method of manufacturing the same.

Recently, the trend of high integration of semiconductor devices is greatly influenced by the development of fine pattern formation technology. In particular, the photoresist pattern is widely used as a mask such as an etching process or an ion implantation process in the manufacturing process of a semiconductor device.

Therefore, miniaturization of the photoresist pattern is essential for high integration of semiconductor devices. The resolution of the photoresist pattern is proportional to the wavelength and process variables of the light source of the reduction exposure apparatus, and inversely proportional to the numerical aperture (NA) of the reduction exposure apparatus. do.

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Degree is the limit.

Therefore, in order to form a fine pattern of 0.5 µm or less, a narrow exposure apparatus using a deep ultra violet, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size and distance from the peripheral wiring, and the aspect ratio, which is a ratio between the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

The contact hole has a misalignment tolerance during mask alignment, lens distortion during exposure process, critical dimention variation during mask fabrication and photolithography process, and between masks to maintain a gap. The mask is formed by considering factors such as registration.

In addition, in order to overcome the limitations of the lithography process in forming the contact hole, a technology for forming the contact hole by a self-aligning method has been developed. The most promising method of forming a self-aligned contact hole is to use a nitride film as an etch barrier.

A method for manufacturing a contact hole of a conventional semiconductor device will be described with reference to FIG. 1.

First, a predetermined well region 2, a device isolation coral film 3, and a gate oxide film 4 are formed on a semiconductor substrate 1, and then a series of gate electrodes 5 are formed on the gate oxide film 4. Form them. At this time, a mask oxide film 6 pattern and a polysilicon layer 7 pattern overlap the upper side of the gate electrode 5 to prevent exposure of the gate electrode 5 when forming a self-aligned contact.

Then, a source / drain electrode 9 having an L.D. (Lightly Doped Drain) structure is formed on both semiconductor substrates 1 of the gate electrode 5 by a conventional method, and the gate electrode After the nitride film spacer 8 is formed on the sidewall of (5), the interlayer insulating film 10 is formed on the entire surface of the structure as an oxide film material.

Thereafter, the interlayer insulating film 10 on the upper portion of the source / drain electrode 9, which is supposed to be a contact, is removed to form a contact hole 15, and the source / drain electrode 9 is formed through the contact hole 15. The upper conductive wiring 11 in contact with the () is formed.

The semiconductor device according to the related art uses polysilicon as an etch barrier layer during an interlayer insulating layer etching process for forming a contact hole, and the source / drain electrode is formed by forming a source / drain electrode with the polysilicon layer pattern exposed. And the polysilicon layer pattern is connected to another contact hole adjacent to each other through the polysilicon pattern formed together with the gate electrode, thereby reducing the reliability and process yield of device operation.

The present invention is to solve the above problems, the object of the present invention is to thermally oxidize the exposed portion after forming the contact hole of the polysilicon layer pattern used as an etch barrier layer in the etching process for forming the self-aligned contact hole The present invention provides a semiconductor device and a method of manufacturing the same, which can prevent a connection to an adjacent contact to improve process yield and reliability of device operation.

Features of the semiconductor device contact according to the present invention for achieving the above object, the gate electrode formed on the semiconductor substrate, the mask insulating film and the polysilicon layer pattern formed by sequentially overlapping the upper side of the gate electrode, A nitride spacer formed on the sidewalls of the mask insulating film pattern and the polycrystalline silicon layer pattern, a source / drain electrode formed on the semiconductor substrate on one side of the gate electrode, and an interlayer formed on the entire surface of the structure. A contact hole exposing the source / drain electrode to be exposed by removing an insulating layer and an interlayer insulating layer on the upper portion of the source / drain electrode, which is intended to be a contact, and exposing one side of the mask insulating layer pattern on the gate electrode; Thermal acid formed on one side of the polysilicon layer pattern in contact with It is provided as a film.

Another feature of a semiconductor device contact according to the present invention includes a gate electrode formed on a semiconductor substrate, a mask insulating film and a polysilicon layer pattern sequentially formed on the upper side of the gate electrode, and the gate electrode and a mask insulating film pattern. And thermally oxidized nitride nitride spacers formed on the sidewalls of the polysilicon layer pattern, source / drain electrodes formed on the semiconductor substrate on one side of the gate electrode, and a portion of the polysilicon layer pattern on the gate electrode. The oxide film, the interlayer insulating film formed on the entire surface of the structure, and the interlayer insulating film on the upper portion of the portion scheduled for contact from the source / drain electrode are removed to expose the source / drain electrode, but the column above the gate electrode A contact hole exposing an oxide film and exposed through the contact hole An oxide film spacer surrounding a thermal oxide film and a nitride film spacer is provided.

According to another aspect of the present invention, there is provided a method of manufacturing a contact for a semiconductor device, the method including forming a gate oxide film on a semiconductor substrate, and forming a gate electrode on the gate oxide film, wherein a mask is formed on the gate electrode. Forming an insulating film pattern and a polysilicon layer pattern overlapping with each other, forming a source / drain electrode on the semiconductor substrate on both sides of the gate electrode, and forming a nitride film spacer on the sidewall of the gate electrode; Forming a contact hole by removing an interlayer insulating film on the upper part of the source / drain electrode, which is intended to be a contact, and exposing one side of the polysilicon layer pattern together; The thermal oxide film is formed by thermally oxidizing one side of the exposed polysilicon layer pattern and the semiconductor substrate. And a step of removing the thermal oxide film on the upper side of the semiconductor substrate, and forming an upper conductive wiring in contact with the source / drain electrodes exposed through the contact hole.

According to another aspect of the present invention, there is provided a method of manufacturing a contact for a semiconductor device, the method including forming a gate oxide film on a semiconductor substrate, and forming a gate electrode on the gate oxide film, wherein a mask insulating film pattern and polysilicon are formed on the gate electrode. Forming a layer pattern so as to overlap each other; forming a source / drain electrode on semiconductor substrates on both sides of the gate electrode; forming a nitride spacer on the sidewall of the gate electrode; and forming an interlayer insulating film on the entire surface of the structure. And forming a contact hole by removing an interlayer insulating film on the upper portion of the source / drain electrode, which is intended to be a contact, and exposing one side of the polysilicon layer pattern together with the exposed polycrystalline silicon. Thermally oxidizing one side of the layer pattern and the semiconductor substrate to form a thermal oxide film; A method of forming an oxide spacer surrounding a thermal oxide film and a nitride film spacer exposed through a contact hole is provided.

Hereinafter, a contact of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a semiconductor device having a contact hole according to a first embodiment of the present invention.

First, a predetermined well region 2 is formed above the portion of the semiconductor substrate 1 that is supposed to be an active region, and an element isolation oxide film 3 is formed on the element isolation region, and the entire surface of the structure. The gate oxide film 4 is formed thereon, and a series of gate electrodes 5 are formed on the gate oxide film 4. In this case, a mask oxide layer 6 pattern and a polysilicon layer 7 pattern overlap each other to prevent exposure of the gate electrode 5 when forming the self-aligned contact.

In addition, a nitride film spacer 8 and a source / drain electrode 9 are formed on the sidewall of the gate electrode 5 and the semiconductor substrate 1 on both sides thereof, and are intended to be in contact with the source / drain electrode 9. An interlayer insulating film 8 having a contact hole 15 exposing a portion thereof is formed on the entire surface of the structure, and the upper conductive wiring contacting the source / drain electrodes 9 through the contact hole 15. (11) is formed.

Here, the thermal oxide film 20 is formed at one side of the polysilicon layer 7 contacting the contact hole 15, and the mask oxide film 6 pattern is exposed at the contact hole 15.

3A to 3D are process charts for manufacturing a contact hole of a semiconductor device according to a first embodiment of the present invention.

First, a well region 2 is formed on a portion of the semiconductor substrate 1 that is intended as an active region, an element isolation oxide film 3 is formed in the device isolation region, and then a gate oxide film ( 4), the first polysilicon layer 5a serving as a gate electrode, the mask oxide film 6 having a thickness of about 10 to 100 nm, and the second polycrystalline silicon layer 7 having a thickness of about 10 to 100 nm serving as an etching barrier are sequentially formed. To form. (See also 3a).

Then, the first polysilicon layer 5a, the mask oxide film 4, and the second polysilicon layer 7 are sequentially patterned by using a gate patterning mask (not shown) to overlap the first polysilicon layer. After the gate electrode 5 having the layer 5a pattern, the mask oxide film 6 pattern, and the second polysilicon layer 7 pattern are formed, the semiconductor substrate 1 on both sides of the gate electrode 3 is provided with a source / A drain electrode 9 is formed, and a nitride film spacer 8b is formed on the sidewalls of the second polysilicon layer 7 pattern, the mask oxide film 6 pattern, and the gate electrode 5. (See also 3b).

Thereafter, the interlayer insulating film 10 is formed on the entire surface of the structure, and the contact hole is sequentially removed by removing the interlayer insulating film 10 and the gate oxide film 4 on the upper portion of the semiconductor substrate 1, which are supposed to be contacts. (15) is formed, and the source / drain electrodes 9 are exposed by forming a self-aligned contact using an etching mask larger than the size actually formed. In this case, the interlayer insulating film 10 may be formed of a TeOs (Tetra etchyl orthor silicate; TEOS) oxide film or Mediuum Temperature Oxide (hereinafter referred to as MTO) having a thickness of about 30 to 100 nm and a BPSG having a thickness of 100 to 300 nm. And sequentially reflow and flatten by reflowing at a temperature of about 700 ~ 900 ℃. Here, one side of the second polysilicon layer 7 pattern is exposed through the contact hole 15. (See also 3c).

Then, the exposed second polysilicon layer 7 pattern is wet thermally oxidized at a low temperature of about 700 to 900 ° C. to form a thermal oxide film 20. At this time, the exposed semiconductor substrate 1 is also oxidized to a predetermined thickness. (See also 3d).

Thereafter, although not shown, the thermal oxide film 20 is removed by a front anisotropic etching method to expose the source / drain electrodes 9 and contact the source / drain electrodes 9 through the contact holes 15. The upper conductive wiring is formed.

4 is a second embodiment of the present invention. As shown in FIG. 2, after forming the thermal oxide film 20, the oxide spacer 25 is formed on the sidewalls of the polycrystalline silicon pattern 7 and the source / drain electrodes 9. ) Is electrically insulated.

In this structure, the thermal oxide film 20 is not etched after the process of FIG. 3d, but the entire surface is coated with an oxide film having a thickness of about 50 to 200 nm, and anisotropically etched to form the spacer 25 and the upper conductive wiring 11 is formed. Yes.

As described above, the semiconductor device contact and the method of manufacturing the same according to the present invention is thermally oxidized after the contact etching process the polysilicon layer pattern deposited on the upper side of the gate electrode for use as an etch barrier in the formation of self-aligned contacts Since the source / drain voltage is prevented from being short-circuited and the short-circuit between adjacent contacts is also prevented, there is an advantage of improving process yield and reliability of device operation.

Claims (10)

A gate electrode formed on the semiconductor substrate, a mask insulating film and a polycrystalline silicon layer pattern sequentially stacked on the upper side of the gate electrode, and a nitride film formed on sidewalls of the gate electrode, the mask insulating film pattern and the polycrystalline silicon layer pattern A spacer, a source / drain electrode formed on the semiconductor substrate on one side of the gate electrode, an interlayer insulating film formed on the entire surface of the structure, and an interlayer insulating film on the upper portion of the portion scheduled for contact from the source / drain electrode. And a contact hole for exposing the source / drain electrodes to expose one side of the mask insulating layer pattern on the gate electrode, and a thermal oxide film formed on one side of the polysilicon layer pattern in contact with the contact hole. Contact. The semiconductor device contact as claimed in claim 1, wherein said mask insulating film is an oxide film or a nitride film. The contact of claim 1, wherein the mask insulating film is 10 to 100 nm thick. The contact of claim 1, wherein the polysilicon layer is 10 to 100 nm thick. 2. The semiconductor device according to claim 1, wherein the interlayer insulating film is formed by filling with a TEOS oxide film having a thickness of 30 to 100 nm or a MTO and a BPSG having a thickness of 100 to 300 nm, and reflowing and flattening at 700 to 900 ° C. Contact. A gate electrode formed on the semiconductor substrate, a mask insulating film and a polycrystalline silicon layer pattern sequentially stacked on the upper side of the gate electrode, and a nitride film formed on sidewalls of the gate electrode, the mask insulating film pattern and the polycrystalline silicon layer pattern A spacer, a source / drain electrode formed on the semiconductor substrate on one side of the gate electrode, a thermal oxide film formed by thermal oxidation of a portion of the polycrystalline silicon layer pattern on the gate electrode, and formed on the entire surface of the structure The interlayer insulating layer and the interlayer insulating layer on the upper portion of the source / drain electrode, which are supposed to be contacts, are removed to expose the source / drain electrodes, and to expose the thermal oxide layer on the gate electrode. Oxide film surrounding thermal oxide film and nitride film spacer exposed through A contact of a semiconductor device having a spacer. Forming a gate oxide film on the semiconductor substrate, forming a gate electrode on the gate oxide film, and forming a mask insulating film pattern and a polysilicon layer pattern on the gate electrode, wherein both sides of the gate electrode Forming a source / drain electrode on the semiconductor substrate, and forming a nitride spacer on the sidewall of the gate electrode; forming an interlayer insulating film on the entire surface of the structure; and contacting the source / drain electrode. Forming a contact hole by removing the interlayer insulating layer on the upper part of the portion, and exposing one side of the polysilicon layer pattern together; and thermally oxidizing one side of the exposed polysilicon layer pattern and the semiconductor substrate. The step of removing the thermal oxide film on the upper side of the semiconductor substrate; Contact method of manufacturing a semiconductor device including a step of forming a top conductive wiring being in contact with the source / drain electrodes, which are exposed through. The method of claim 7, wherein the thermal oxidation process is wet thermally oxidized at 700 to 900 ° C. 9. Forming a gate oxide film on the semiconductor substrate, forming a gate electrode on the gate oxide film, and forming a mask insulating film pattern and a polysilicon layer pattern on the gate electrode, wherein both sides of the gate electrode Forming a source / drain electrode on the semiconductor substrate, and forming a nitride spacer on the sidewall of the gate electrode; forming an interlayer insulating film on the entire surface of the structure; and contacting the source / drain electrode. Forming a contact hole by removing the interlayer insulating layer on the upper part of the portion, and exposing one side of the polysilicon layer pattern together; and thermally oxidizing one side of the exposed polysilicon layer pattern and the semiconductor substrate. And a thermal oxide film and a nitride film spacer exposed through the contact hole. A method of manufacturing a contact for a semiconductor device comprising the step of forming an oxide film spacer surrounding the. 12. The method of claim 10, wherein the oxide spacer forming step is formed by applying an anisotropic etching process on the entire surface of the oxide film having a thickness of 50 to 200 nm.