JP2691153B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, in particular, a method for manufacturing a high-speed / highly-integrated transistor and the like, in which a trench isolation and a thick oxide film other than an active region are formed in a self-aligned manner. A process for forming a nitride film (13) for selective oxidation and a film (15) for groove formation on a semiconductor substrate for the purpose of providing a method for manufacturing a semiconductor device that can be miniaturized and shorten the process. And a step of etching the film for forming the groove using a peripheral etching technique and then etching the nitride film and the substrate using the film as a mask to form a groove in the substrate, and a step of side-etching the nitride film. And a step of thermally oxidizing the surface of the semiconductor substrate and the inside of the groove after the side etching to form a field oxide film and a groove separation.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high speed / highly integrated transistor and the like.

[Conventional technology]

In recent years, in the field of semiconductor device manufacturing, in response to the high performance of bipolar transistors and MOS transistors,
In order to avoid speed reduction due to miniaturization and PN junction isolation capacity, trench isolation is often used. This groove separation is caused by reactive ion etching [RI
E (Reactive Ion Etching)] is used to dig a narrow groove in the silicon by directional etching, and the groove is filled with an insulator for separation. Further, in order to reduce the capacitance between the wiring and the substrate, it is necessary to form a thick oxide film in the field region except the active region. Therefore, in order to miniaturize and speed up the semiconductor device in the future, it is necessary to form the trench isolation and the field oxide region in a self-aligned manner.

5 (a) to 5 (c) are cross-sectional views of the conventional U-groove isolation and manufacturing process of the field oxide film region.

As shown in FIG. 3A, the nitride film 2 deposited on the silicon substrate 1 is patterned by a lithography technique by a normal selective oxidation (LOCOS) method, and then thermal oxidation is performed to form a thick field oxide film 3 region. To do.

Next, as shown in FIG. 2B, after removing the nitride film 2, a phosphorus glass (PSG) film 4 and a resist film 5 are formed,
The phosphorus glass (PSG) film 4 is etched by RIE using the resist film 5 after removing the resist film on the U groove formation region by the lithography technique as a mask.

Next, as shown in FIG. 3C, the field oxide film 3 and the silicon substrate 1 are further etched to form a U groove 6.

After this step, the U trench 6 is filled with, for example, polysilicon to perform U trench isolation (trench isolation).

[Problems to be solved by the invention]

In the prior art, masks are used for separating the U-groove and for forming the field oxide film 3 region, and as shown in FIG. 5 (b), necessary intervals (2α ), The position deviation (β) considering the alignment margin of the U-groove etching mask
It was necessary to make a layout that added. That is, U
Since the trench isolation and the field oxide film 3 region are not formed in self-alignment, a (2α + β) alignment margin is required, which imposes restrictions on miniaturization. Further, when the distance between the U groove 6 and the field oxide film 3 becomes submicron due to high integration of the device, the positional deviation cannot be ignored, and U
Occurrence of a defect in which the groove 6 and the end of the field oxide film 3 overlap with each other may occur, resulting in a defect.

Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a thick oxide film other than the trench isolation and the active region is formed in a self-aligned manner to achieve miniaturization and shorten the process.

[Means for Solving the Problems] The above-mentioned problem is a step of forming a nitride film for selective oxidation and a film for forming a groove on a semiconductor substrate, and etching the film for forming the groove using a peripheral etching technique. After that, the step of etching the nitride film and the substrate with the film as a mask to form a groove in the substrate, the step of side etching the nitride film, and the step of thermally oxidizing the semiconductor substrate surface and the groove after the side etching. And a step of forming a field oxide film and a trench isolation.

[Action]

In the present invention, the film for forming the groove is etched only in the peripheral portion by using the peripheral etching technique, so that the submicron groove is formed by the photolithography technique of the rule of 1 μm and the groove and the field oxide are formed by using one mask. The film region can be formed in a self-aligned manner. Therefore, there is no need to use two masks and a margin for aligning the masks as in the conventional case, the pattern can be miniaturized, and the process is shortened as compared with the conventional process of filling the trench with polysilicon. To be done.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the drawings.

1A to 1H are cross-sectional views of manufacturing steps of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1 (a), the surface of the silicon substrate 11 is lightly oxidized to form a thin thermal oxide film (SiO _{2 of} about 100 to 300 Å).
Film) 12, a nitride film (Si ₃ N ₄ film) 13 for selective oxidation having a film thickness of about 500 to 1500 Å is deposited thereon, and a phosphorus glass having a film thickness of about 0.5 to 1 μm is formed thereon. Membrane (PSG membrane) 14,
Further thereon, a molybdenum silicide film (MoSi ₂ film) 15 having a film thickness of about 0.5 to 1 μm is deposited.

Next, as shown in FIG. 1B, a resist film 16 is formed on the MoSi ₂ film 15, and the resist film 16 on the trench formation region is removed by patterning.

Next, as shown in FIG. 1 (c), CCl ₄ / O ₂ (60 to 70
%) Gas composition, the MoSi ₂ film 15 is etched only around the resist film 16, which is a so-called peripheral etching effect. At this time, by controlling the etching time, for example,
A desired fine groove width of about 0.3 μm to 0.5 μm can be obtained. FIG. 2 is a plan view of FIG. 1 (c) of the embodiment of the present invention, in which Mo around the transistor region 17 formed in a rectangular shape is used.
The Si ₂ film 15 is etched (peripheral etching). Further, FIG. 3 is an enlarged sectional view taken along the line AA of FIG. 2, and the MoSi ₂ film 15 is etched from the periphery of the resist film 16 by a predetermined groove width (1). Further, the groove width (l) of this etching and the etching time (t) have a substantially linear proportional relationship as shown in FIG. 5, and by controlling the etching time (t), for example, 0.2 μm to 1.0 μm can be obtained.
An arbitrary groove width of about m can be formed with good controllability.

Next, as shown in FIG. 1 (d), after removing the resist film 16, the PSG film 14 and the Si ₃ N ₄ film 1 using the MoSi ₂ film 15 as a mask.
3. The SiO ₂ film 12 is etched by RIE using a fluorine (F) -based gas such as CF ₄ / O ₂ . At this time, PSG film 14, Si ₃ N
_{The 4} film 13 and the SiO ₂ film 12 are also etched to some extent, but since the etching rate of silicon is about 10 times that of these films and they are formed to have a constant film thickness, they serve as a mask to a predetermined depth.

Next, as shown in FIG. 1 (e), the silicon substrate 11 is switched to a chlorine (Cl) -based gas to etch the silicon substrate 11 to a depth of, for example, about 4 to 5 μm to form a U groove 18 for separation.

Next, as shown in FIG. 1 (f), using hot phosphoric acid,
The Si ₃ N ₄ film 13 is side-etched at a temperature of 160 ° C. or lower using the PSG film 14 as a mask. This side etching amount is
It determines the trench-field oxidation region, and in this case 0.5 μm to 1 μm is suitable.

Next, as shown in FIG. 1 (g), the PSG film 14 is washed out using diluted hydrofluoric acid (HF).

Next, as shown in FIG. 1 (h), thermal oxidation is performed to form an oxide layer.
Form 19. The amount of oxidation is about 6000Å. At this time,
When the groove width is 0.3 μm, the U groove 18 is filled with the oxide layer 19 due to volume expansion due to silicon oxidation, and the U groove 18 is closed. That is, the U-groove isolation and the thick field oxide region are formed by the thermal oxidation.

If further flatness of the U groove 18 is required,
An SOG (Spin On Glass) film may be formed, or a film of phosphorus glass (PSG), boron phosphorus glass (BPSG) or the like may be formed and reflowed by heat treatment, and then etched back.

In the above semiconductor manufacturing method, the fine U groove 18 is formed by using peripheral etching, and then the nitride film 13 for selective oxidation is side-etched by a desired amount from the end of peripheral etching, and then thermally oxidized. For U groove
The isolation by 18 and the thick field oxide region are formed in a self-aligned manner. Therefore, the use of two masks and the alignment margin are no longer required as in the conventional method, and it is possible to miniaturize by that amount, and the process is compared with the conventional process in which the trench is filled with polysilicon. Could be shortened.

In the present invention, the width of the U groove 18 can be arbitrarily set by controlling the amount of peripheral etching, and the field region can be determined by the width of the U groove 18 and the amount of side etching. The scope of application is not limited to the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, fine grooves are formed by using peripheral etching, and then the nitride film for selective oxidation is side-etched by a desired amount from the end of peripheral etching, and then thermally oxidized. Not only can the trench isolation and the field oxide film be formed in a self-aligned manner for miniaturization, but also the process can be shortened.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process according to an embodiment of the present invention, FIG. 2 is a plan view of FIG. 1 (c) of an embodiment of the present invention, and FIG. 3 is an enlarged sectional view taken along line AA of FIG. FIG. 5 is a diagram showing the relationship between the peripheral etching width and time in the embodiment of the present invention, and FIG. 5 is a sectional view of the manufacturing process of the conventional example. In the figure, 11 is a silicon substrate, 12 is a thermal oxide film, 13 is a Si ₃ N ₄ film, 14 is a PSG film, 15 is a MoSi ₂ film, 16 is a resist film, 17 is a transistor region, 18 is a U groove, and 19 is Shows the oxide layer.

Claims (1)

(57) [Claims] 1. A step of forming a nitride film (13) for selective oxidation and a film (15) for forming a groove on a semiconductor substrate (11), and the film for forming the groove (15) is subjected to a peripheral etching technique. A step of forming a groove (18) in the substrate (11) by etching the nitride film (13) and the substrate (11) using the film (15) as a mask after etching using the nitride film (13) Of the semiconductor substrate (11) and the inside of the groove (18) are thermally oxidized after the side etching to form a field oxide film and groove separation. Method.