JPS6235459U - - Google Patents
Info
- Publication number
- JPS6235459U JPS6235459U JP12554385U JP12554385U JPS6235459U JP S6235459 U JPS6235459 U JP S6235459U JP 12554385 U JP12554385 U JP 12554385U JP 12554385 U JP12554385 U JP 12554385U JP S6235459 U JPS6235459 U JP S6235459U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- output
- signal
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案による一実施例を示すブロツク
図、第２図は同上を説明するタイムチヤート、第
３図は第１図の回路を使用した全体の回路を示す
ブロツク図であり、第４図は従来例を示すブロツ
ク図である。
１，２，４……フリツプフロツプ、３……プリ
セツト付のフリツプフロツプ、５……アンドゲー
ト（論理積手段）。
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart explaining the same, FIG. 3 is a block diagram showing the entire circuit using the circuit of FIG. 1, and FIG. The figure is a block diagram showing a conventional example. 1, 2, 4...Flip-flop, 3...Flip-flop with preset, 5...AND gate (logical product means).
Claims (1)
らびに書き込み補償信号をそれぞれ入力して磁気
デイスク装置へのデータ書き込みを補償する回路
において、 前記書き込みデータを入力遅延して出力する直
列接続の第１ならびに第２のフリツプフロツプと
、 前記書き込み補償信号をプリセツト入力すると
共に、前記第１のフリツプフロツプの反転出力信
号をクロツクとする第３のフリツプフロツプと、 前記第１のフリツプフロツプの出力信号と、前
記第１ならびに第２フリツプフロツプのクロツク
を反転した信号との論理積をとる手段と、 前記第３のフリツプフロツプの出力を前記論理
積手段の出力でサンプリングして書き込み補償信
号を出力する第４のフリツプフロツプと、を有す
ることを特徴とする磁気デイスク装置の書き込み
補償回路。[Scope of Utility Model Registration Claim] In a circuit that compensates for data writing to a magnetic disk device by inputting a write data signal and a write compensation signal output from a controller, there is provided a series-connected circuit that inputs and outputs the write data after input delay. first and second flip-flops; a third flip-flop to which the write compensation signal is preset input and clocked by the inverted output signal of the first flip-flop; an output signal of the first flip-flop; a fourth flip-flop that samples the output of the third flip-flop with the output of the AND means and outputs a write compensation signal; A write compensation circuit for a magnetic disk device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12554385U JPS6235459U (en) | 1985-08-15 | 1985-08-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12554385U JPS6235459U (en) | 1985-08-15 | 1985-08-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6235459U true JPS6235459U (en) | 1987-03-02 |
Family
ID=31018529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12554385U Pending JPS6235459U (en) | 1985-08-15 | 1985-08-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6235459U (en) |
-
1985
- 1985-08-15 JP JP12554385U patent/JPS6235459U/ja active Pending
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