JPS6234141B2 - - Google Patents
Info
- Publication number
- JPS6234141B2 JPS6234141B2 JP56127048A JP12704881A JPS6234141B2 JP S6234141 B2 JPS6234141 B2 JP S6234141B2 JP 56127048 A JP56127048 A JP 56127048A JP 12704881 A JP12704881 A JP 12704881A JP S6234141 B2 JPS6234141 B2 JP S6234141B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- hole
- tape carrier
- wiring pattern
- metal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56127048A JPS5828862A (ja) | 1981-08-13 | 1981-08-13 | テ−プキヤリア |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56127048A JPS5828862A (ja) | 1981-08-13 | 1981-08-13 | テ−プキヤリア |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63099776A Division JPS63288038A (ja) | 1988-04-22 | 1988-04-22 | テープキャリア |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5828862A JPS5828862A (ja) | 1983-02-19 |
JPS6234141B2 true JPS6234141B2 (enrdf_load_stackoverflow) | 1987-07-24 |
Family
ID=14950312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56127048A Granted JPS5828862A (ja) | 1981-08-13 | 1981-08-13 | テ−プキヤリア |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5828862A (enrdf_load_stackoverflow) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59161848A (ja) * | 1983-03-04 | 1984-09-12 | Nec Corp | 樹脂封止型半導体装置の製造装置 |
JPH056659Y2 (enrdf_load_stackoverflow) * | 1987-11-17 | 1993-02-19 | ||
US4980219A (en) * | 1988-04-06 | 1990-12-25 | Casio Computer Co., Ltd. | Carrier tape for bonding IC devices and method of using the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5327364A (en) * | 1976-08-26 | 1978-03-14 | Fujitsu Ltd | Film carrier integrated circuit and its production |
JPS5410867A (en) * | 1977-06-25 | 1979-01-26 | Toyota Motor Corp | Brake booster for vehicle |
JPS54155869A (en) * | 1978-05-29 | 1979-12-08 | Seiko Epson Corp | Crystal watch |
-
1981
- 1981-08-13 JP JP56127048A patent/JPS5828862A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5828862A (ja) | 1983-02-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6448783B1 (en) | Method of inspecting semiconductor chip with projecting electrodes for defects | |
US6756606B2 (en) | Apparatus and method for marking defective sections of laminate substrates | |
US5263240A (en) | Method of manufacturing printed wiring boards for motors | |
JPS6234141B2 (enrdf_load_stackoverflow) | ||
JP4336151B2 (ja) | テープキャリア型の半導体装置 | |
US6143355A (en) | Print alignment method for multiple print thick film circuits | |
JPH02224354A (ja) | 半導体装置のコンタクトホールの目ずれ検査方法 | |
US6514777B2 (en) | Built-in inspection template for a printed circuit | |
JPH02198186A (ja) | プリント配線板シールド層検査方法と検査手段 | |
JPS63288038A (ja) | テープキャリア | |
JP2654600B2 (ja) | 試験用端子兼用型部品搭載位置認識マーク | |
JPS63261842A (ja) | 集積回路とその製造方法 | |
JPH065674A (ja) | 半導体集積回路装置 | |
JPS6116029B2 (enrdf_load_stackoverflow) | ||
JP3437467B2 (ja) | 半導体装置の検査方法 | |
JPH0720587Y2 (ja) | プリント基板のハンダブリッジ検査シート | |
JPH01319956A (ja) | 半導体集積回路 | |
JPS62239039A (ja) | プリント回路板検査装置 | |
JPS5927095B2 (ja) | フルオ−トワイヤボンディングのパタ−ン検出方法 | |
US8164168B2 (en) | Semiconductor package | |
JPH02278787A (ja) | プリント配線基板のパターン構造 | |
JPH0621180A (ja) | プリント配線板のソルダーレジスト層の位置ずれ検査方法 | |
JPS6218037Y2 (enrdf_load_stackoverflow) | ||
JPS633499A (ja) | 電子部品の装着状態検出方法 | |
JPH01218037A (ja) | 半導体ウェハの検査方法 |