JPS623364A - バス占有制御方式 - Google Patents

バス占有制御方式

Info

Publication number
JPS623364A
JPS623364A JP14164785A JP14164785A JPS623364A JP S623364 A JPS623364 A JP S623364A JP 14164785 A JP14164785 A JP 14164785A JP 14164785 A JP14164785 A JP 14164785A JP S623364 A JPS623364 A JP S623364A
Authority
JP
Japan
Prior art keywords
bus
signal
usage
request
requesting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14164785A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0433065B2 (enrdf_load_stackoverflow
Inventor
Toshiharu Oshima
大島　俊春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14164785A priority Critical patent/JPS623364A/ja
Publication of JPS623364A publication Critical patent/JPS623364A/ja
Publication of JPH0433065B2 publication Critical patent/JPH0433065B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
JP14164785A 1985-06-28 1985-06-28 バス占有制御方式 Granted JPS623364A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14164785A JPS623364A (ja) 1985-06-28 1985-06-28 バス占有制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14164785A JPS623364A (ja) 1985-06-28 1985-06-28 バス占有制御方式

Publications (2)

Publication Number Publication Date
JPS623364A true JPS623364A (ja) 1987-01-09
JPH0433065B2 JPH0433065B2 (enrdf_load_stackoverflow) 1992-06-02

Family

ID=15296908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14164785A Granted JPS623364A (ja) 1985-06-28 1985-06-28 バス占有制御方式

Country Status (1)

Country Link
JP (1) JPS623364A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01211155A (ja) * 1988-02-19 1989-08-24 Hitachi Ltd データ転送制御装置
JPH03142650A (ja) * 1989-10-23 1991-06-18 Internatl Business Mach Corp <Ibm> 優先使用遅延回路
JPH04323755A (ja) * 1991-04-24 1992-11-12 Matsushita Electron Corp Ｄｍａ装置
USRE40261E1 (en) 1996-03-04 2008-04-22 Matsushita Electric Industrial Co., Ltd. Apparatus and method of partially transferring data through bus and bus master control device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166534A (en) * 1980-05-27 1981-12-21 Mitsubishi Electric Corp Simultaneous selection preventing circuit
JPS59223827A (ja) * 1983-06-03 1984-12-15 Hitachi Micro Comput Eng Ltd バスア−ビトレ−シヨン回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166534A (en) * 1980-05-27 1981-12-21 Mitsubishi Electric Corp Simultaneous selection preventing circuit
JPS59223827A (ja) * 1983-06-03 1984-12-15 Hitachi Micro Comput Eng Ltd バスア−ビトレ−シヨン回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01211155A (ja) * 1988-02-19 1989-08-24 Hitachi Ltd データ転送制御装置
JPH03142650A (ja) * 1989-10-23 1991-06-18 Internatl Business Mach Corp <Ibm> 優先使用遅延回路
JPH04323755A (ja) * 1991-04-24 1992-11-12 Matsushita Electron Corp Ｄｍａ装置
USRE40261E1 (en) 1996-03-04 2008-04-22 Matsushita Electric Industrial Co., Ltd. Apparatus and method of partially transferring data through bus and bus master control device

Also Published As

Publication number Publication date
JPH0433065B2 (enrdf_load_stackoverflow) 1992-06-02

Similar Documents

Publication Publication Date Title
US6986005B2 (en) Low latency lock for multiprocessor computer system
US4719567A (en) Method and apparatus for limiting bus utilization
JP2003186824A (ja) バス使用権優先度調整装置およびシステム
JPS623364A (ja) バス占有制御方式
JPH04283805A (ja) マイクロプロセッサシステムを動作させるための装置
JP2908147B2 (ja) バス制御装置及び方法
CA2021826A1 (en) Delay logic for preventing cpu lockout from bus ownership
JPS62154045A (ja) バス調停方式
JPH03263158A (ja) 共通バス調停制御方式
EP0987635A3 (en) Apparatus and method for limit -based arbitration scheme
JPH0525135B2 (enrdf_load_stackoverflow)
JPH05324543A (ja) バス・アービタ装置
JPS6160162A (ja) バス調停方式
JPS59231952A (ja) マルチプロセツサ間通信制御方式
JPH0156420B2 (enrdf_load_stackoverflow)
JPS62236058A (ja) バス獲得方式
JPH08297631A (ja) バス制御方法
JPH08263428A (ja) スプリット転送方式を適用する情報処理装置及び同装置におけるバス調停方法
JPH0353362A (ja) データ処理システムの階層バス制御装置
JPH0716235U (ja) 情報処理システム
JPH0338761A (ja) バス競合整理方式
JPH023851A (ja) ダイレクトメモリアクセス装置
JPH0587647U (ja) バス調停回路
JPS63231662A (ja) バス制御回路
JPS5850047A (ja) 資源競合制御方式