JPS6232547A - State reading-out and writing circuit for information processor - Google Patents

Abstract

PURPOSE:To make it unnecessary to provide an exclusive read-out path by constituting the titled device so that the first register selects information which is set in the course of its original operation at the time of a regular operation, and after a scan-in operation, the second register is selected and an output is provided to the first register. CONSTITUTION:A register 1 is a register for holding the state of other device, for instance, stop-run of a clock, diagnostic/regular modes, etc., a register 3 is an internal register of a state reading-out/writing circuit 6 of an information processor, and as for a register 2, when the register 1 is brought to a shift operation, an influence is exerted on other device, therefore, in its regular operation state, it has the same contents as those of the register 1, and can use a scan path in the same way as the register 3, when reading out or writing an internal state of a device. A selector 4 is provided for two inputs and four circuits, selects signal lines 108-111 when a signal line 103 is logic '0', selects signal lines 120-123 at the time of logic '1', and provides an output.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement of an internal state successive/write circuit in an information processing device.

(Prior art) Conventionally, registers consisting of flip-flops that are not incorporated in a scan path have a separate read-only path, and are edited and displayed separately from flip-flops connected in other scan paths. was.

(Problem to be Solved by the Invention) In the conventional information processing device described above, when a flip-flop is connected to the scan path, its contents are shifted by one bit each time the clock is incremented, so that the output of the flip-flop is shifted by one bit. There may be flip-flops that control states and may enter states that are prohibited in normal operation.

In such a case, it is necessary to provide a read-only bus,
This display requires an editing program separate from the flip-flop having a scan path, and has the disadvantage that writing during diagnosis or debugging cannot be executed.

The object of the present invention is to have a first register consisting of a plurality of flip-flops that holds the state of other devices and cannot be connected to the scan path, and a first register that normally holds the same contents as the first register. It is connected to the scan path and reads the internal state by stepping the clock.
and a second register consisting of a plurality of 70 flips that can be written to.During normal operation, the first register selects the state information to be set during the original operation, and after the scan operation, the second register selects the state information to be set during the original operation. An object of the present invention is to provide a status read/write circuit for an information processing device configured to eliminate the above-mentioned drawbacks by selecting a register and outputting it to a first register, and eliminating the need to provide a read-only path. .

(Means for Solving the Problems) A state read/write circuit of an information processing device according to the present invention is configured to include first and second registers and a selector.

The first register holds the status of other devices and cannot be connected to the scan path.

The second register normally holds the same contents as the first register and is connected to the scan path so that internal state information can be read/written by advancing the clock.

During normal operation, the selector selects the state information that should be set in the first register during its original operation, and after the scan-in operation, selects the second selector and outputs it to the first register. .

(Example) Next, the present invention will be explained with reference to the drawings.
FIG. 1 is a block diagram showing an example of an integrated circuit. 1st
In the figure, 1 to 3 are registers, 4 is a selector, 5 is a control circuit, and 6 is a status read/write circuit of the information processing device.

In FIG. 1, register 1 is a register that holds the status of other devices, such as clock stop/running, diagnosis/normal mode, etc. Normally, data on signal lines 108 to 111 is set in register 1, and the signal It is sent to other devices via lines 116-119. The register 3 is an internal register of the status read/write circuit 6 of the information processing device,
The contents of register 3 are input to the arithmetic unit, and its output does not disturb the status of other devices. Register 2 affects other devices when register 1 is shifted, so in normal operating conditions, register 2 is kept the same as register 1, and when the internal state of the device is read or written, register 3 is used. This allows you to use scan paths in the same way as . The selector 4 has four circuits powered by two people, and when the signal line 103 is in logic O (shift mode), the signal #j! 108 to 111 are selected, and when the logic is 1 (shift mode), signal lines 120 to 123 are selected and output. The control circuit 5 controls the clocks and shift mode terminals of the registers 1 to 3, as well as the select signal of the selector 4.

FIG. 2 is an explanatory diagram showing in detail the operations of registers 1 to 3 in FIG. 1. Registers 1 to 3 operate in synchronization with the clock. In 8FT-0 (normal usage mode, not shift mode), if HLD=O, input data is set internally and output as is, and HLD-
If it is 1, the internal state will not change and the output will not change either. When 5FT=1 (shift mode), the value of the 8I (shift in) terminal is taken in and shifted one bit at a time regardless of HLD.

3 and 4 are timing charts showing the operation of the status read/write circuit of the information processing device of FIG. 1, respectively. The operation will be described in detail below with reference to FIGS. 3 and 4.

In Figure 3: 1. -1. In this case, registers 1 to 3 are in a normal operating state and shift mode=0. At this time, the contents of register 2 match the contents of register 1. After t, the shift mode=H, and when the clock is advanced, the internal state is shifted one bit at a time. This information is finally read out to the control circuit 5 through the signal line 120.

FIG. 4 shows a shift-in operation for returning the data read in FIG. 3 to its original state or setting an arbitrary value to an arbitrary register.

When the data to be written is serially input to the signal line 1064 and the clock is stepped, the data is shifted in the shift bus in the same manner as in FIG. When the clock is advanced by exactly the number of flips 70 to be shifted and the clock is sent to register 1, signal lines 120 to 120
Register 2 is selected by selector 4 which selects 123.
The contents of register 1ζ are set, and any value can be set in register 1 without disturbing the status of other devices during shifting.

(Effects of the Invention) As explained above, the present invention has a first register that holds the status of other devices and cannot be connected to the scan path, and a first register that normally holds the same contents and cannot be connected to the scan path. and a second register whose internal state can be read/written by incrementing the clock.During normal operation, the first register selects information that is set during normal operation. , after the scan-in operation, by selecting the second register and outputting it to the first register, the contents of the register that could not be incorporated into the scan path because it is in a prohibited state can be
Having a register to store the copy has the effect of making it possible to read/write the state information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a status read/write circuit of an information processing apparatus according to the present invention. FIG. 2 is a state explanatory diagram illustrating an example of the operation of the register in FIG. 1. 3 and 4 are timing charts showing an example of the operation of the register shown in FIG. 1, respectively. 1-3...Register 4...Selector 5...Control device 6...Information processing device 101-131.
··Signal line

Claims (1)

[Claims] A first register that holds the state of other devices and cannot be connected to the scan path, and a first register that normally holds the same contents as the first register and is connected to the scan path and advances the clock. A second register is configured to read/write internal state information, and during the normal operation, the first register selects the state information to be set during the original operation, and after the scan-in operation, the first register selects the state information to be set during the normal operation. 1. A state read/write circuit for an information processing device, comprising: a selector for selecting one of the two selectors and outputting the selected selector to the first register.