JPS6231443A - Input and output processor - Google Patents

Abstract

PURPOSE:To attain a self-diagnosis over a wide range by using a transmission preventing FF for desired data, a data transfer starting FF, etc. CONSTITUTION:The microprocessor 31 of the MPU 3 of an input/output processor 2 transmits an input transfer instruction signal and an input transfer start instruction signal based on a self-diagnosis program. Then data are transferred to the data buffer 32 of the MPU 3 from the corresponding data buffer 41 of an IPU 4. In this case, the preventing FF 33a of a data buffer control part 33 is set and therefore the input data are not written to a main memory device 1 and preserved in the buffer 32 to undergo the check of the justifiability through the processor 31. Then the self-diagnosis is given to an input data transfer path and the transfer control function. While an FF 42a which suppresses the output is added together with an FF 33b which starts the transfer of data for both MPU 3 and IPU 4. Thus the self-diagnosis is possible over a wide range including the data transfer path, the transfer control function, the simultaneous working function, etc. without using any complicated constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output processing device used in an information processing device, and particularly to a self-diagnosis method for the input/output processing device.

[Conventional technology]

Generally speaking, an input/output processing device is self-diagnosed by test firmware resident in the input/output processing device when the input/output processing device is initialized.

The target of this self-diagnosis is a functional test of microinstructions.

Tests are mainly performed by writing/reading registers and buffers.

[Problem to be solved by the invention] In the case of the above-mentioned input/output processing device, the scope of self-diagnosis is limited, and the data transfer route which requires a large amount of hardware,
There is a problem that the data transfer control function, simultaneous operation function, etc. have not been tested, and the failure detection rate by self-diagnosis is low.

[Failure to solve the problem]

The present invention includes a plurality of input/output device control sections that respectively control a plurality of input/output devices, and a centralized control section that centrally controls the plurality of input/output device control sections, and the centralized control section includes the plurality of input/output devices. A plurality of first
A data buffer section is provided, and a second data buffer section is provided for each of the plurality of input/output device control sections.

In an input/output processing device that performs data buffering control, an inhibit flip-flop that inhibits data transfer from the first data buffer section to the main storage device; an inhibition flip-flop for inhibiting data transfer; and an activation control flip-flop for simultaneously activating data transfer between the first data buffer section and the second data buffer section, and for initializing the input/output processing device. An input/output processing device characterized in that, at times, a self-diagnosis of a data transfer path, a transfer control function, and a simultaneous operation function between the first data buffer section and the second data buffer section is performed. be.

〔Example〕

The present invention will be explained below with reference to Examples.

The drawing is a block diagram showing one embodiment of the present invention.

Referring to the drawings, 1 is a main storage device, 2 is an input/output processing device, and 5 is an input/output device. The input/output processing device 2 includes a central control unit (MPU) that centrally controls the input/output device control unit (IPU).
) 3 and a plurality of input/output device control units (IPUs) 4 that control the plurality of input/output devices 5, respectively.

The MPU 3 is a program storage type microprocessor 31.in which a self-diagnosis program is stored. A plurality of data buffer sections 32 corresponding to each IPU 4, and a data buffer control section 33 that controls these data buffer sections.
This data buffer control unit 33 includes an inhibit flip-flop f33a that inhibits writing from the data buffer unit 32 to the main storage device 1, and simultaneously activates data transfer with the IPU 4 as described later. An activation control flip-flop 33b is provided.

Each IPU 4 is provided with a data buffer section 41 corresponding to the data buffer section 32 of the MPU 3, and this data buffer section 41 is connected to the data buffer control section 4.
It is controlled by 2. The data buffer control section 42 is provided with a suppressing flip-flop 42a for suppressing data transmission from the data buffer section 41 to the input/output device 5.

The microprocessor 31 of the MPU 3 exchanges information with each IPU 4 via the information exchange path 201.
The data buffer unit 32 of the MPU 3 sends and receives data to and from the data buffer unit 41 of each IPU 4 via the data transfer bus 202.

Here, with reference to one drawing, a self-diagnosis operation by a self-diagnosis program resident in the microprocessor when the input/output processing device 2 is initialized will be described.

The data buffer unit 32 of the MPU 3 and the data buffer unit 41 of the IPU 4 during initialization of the input/output processing device 2
In data transfer between the microprocessor 31 and the IPU 4, the microprocessor 31 first sends an input or output transfer instruction signal to the data buffer control section 42 of a predetermined IPU 4 in an order predetermined by the self-diagnosis program. In the case of an input transfer instruction signal, the data buffer control unit 42 sets data indicating status information of the IPU 4 (hereinafter referred to as input data) in the data buffer unit 41. On the other hand, in the case of an output transfer instruction, the data buffer control unit 42 sets the inhibition flip-flop 42a that inhibits data transmission to the input/output device 5.

Next, the microprocessor 31 sends an input or output transfer instruction signal to the data buffer control section 32 of the MPU 3. In the case of an input transfer instruction signal, the data buffer control unit 33 controls the inhibit flip-flop f33 to inhibit data writing from the data buffer unit 32 to the main storage device 1.
Set a. on the other hand.

In the case of the output transportation instruction signal, the data/gusso control unit 33
is the data manager section 32 corresponding to the above-mentioned IPU 4.
Data indicating status information (hereinafter referred to as output data) issues an output transfer start instruction signal and is executed by the bargeware based on the priority according to the start control fritsoflosop 33b program of the data buffer control unit 33.Input transfer from the microprocessor 31 An instruction signal and an input transfer start instruction signal are sent, and thereby the human data is transferred from the data buffer section 41 of a predetermined IPU 4 to the data buffer section 32 of the corresponding MPU 3 via the data transfer path 202. At this time, since the inhibition flip floor 7' 33a of the data buffer control section 33 is set, the input data is stored and saved in the data buffer section 32 without being written to the main storage device 1. When the processor 31 receives a data transfer completion report from the data/gusso control unit 33, it reads the contents of the input data from the data buffer unit 32 and checks the validity of the input data based on a self-diagnosis program.

Similarly, an output transfer instruction signal and an output transfer start instruction signal are sent from the microprocessor 31.

As a result, output data is transferred from the data buffer unit 32 of the MPU 3 to the data buffer 41 of the corresponding IPU 4 via the data transfer path 202.

At this time, since the inhibit flip-flop 42a of the data buffer control section 42 is set, the output data is stored and saved in the data buffer section 41 without being outputted to the input/output device 5I/il. When the microprocessor 31 receives the data transfer completion report from the data buffer control unit 33, it reads the contents of the output data from the data buffer unit 41 and checks the validity of the output data based on a self-diagnosis program. In this way, each I
The data transfer path, transfer control function, and simultaneous operation function between the PU 4 and the MPU 3 are often diagnosed. Note that input/output data transfer activation instructions and data for the data buffer control units 33 and 42 of the microprocessor 31 are The operation of reporting the completion of data transfer from the buffer control unit 33 to the microprocessor 31 is performed in the same manner as during normal operation of the input/output processing device.

〔Effect of the invention〕

As explained above, according to the input/output processing device according to the present invention, the data transmission inhibiting flip-flop to the main storage device, the data transmitting inhibiting flip-flop to the input/output device, and the activation of the data transfer between the MPU and the IPU are activated. By providing flip-flops that can be activated and activated at the same time, it is possible to diagnose the data transfer path between the data buffers of the MPLT and the IPU, the transfer control function, and the simultaneous operation function.

[Brief explanation of the drawing]

The drawing is a block diagram showing one embodiment of the present invention. 1... Main storage device, 2... Input/output processing device, 3...
・IPU centralized control unit (MPU), 4... Input/output device control unit (IPU'), 5... Input/output device, 31.
...Microprocessor, 32...Data buffer corresponding to each IPU. 33...Data buffer control unit, 41...IPU data buffer, 42...IPU data buffer control unit.

Claims (1)

[Claims] 1. A plurality of input/output device control units that respectively control a plurality of input/output devices, and a centralized control unit that centrally controls the plurality of input/output device control units; A plurality of first data buffer sections each corresponding to the device control section are provided, and a second data buffer section is provided for each of the plurality of input/output device control sections, and data buffering control is performed. In the output processing device, an inhibit flip-flop that inhibits data transfer from the first data buffer section to the main storage device;
a suppressing flip-flop for suppressing data transfer from the second data buffer unit to the input/output device;
an activation control flip-flop that simultaneously activates data transfer between the data buffer section and the second data buffer section; An input/output processing device characterized in that self-diagnosis of a data transfer path to a data buffer section, a transfer control function, and a simultaneous operation function is performed.