JPS6229834B2 - - Google Patents

Info

Publication number
JPS6229834B2
JPS6229834B2 JP16892582A JP16892582A JPS6229834B2 JP S6229834 B2 JPS6229834 B2 JP S6229834B2 JP 16892582 A JP16892582 A JP 16892582A JP 16892582 A JP16892582 A JP 16892582A JP S6229834 B2 JPS6229834 B2 JP S6229834B2
Authority
JP
Japan
Prior art keywords
data
data processing
processing
processing device
pos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16892582A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5958577A (ja
Inventor
Hiroshi Tanaka
Susumu Masumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57168925A priority Critical patent/JPS5958577A/ja
Publication of JPS5958577A publication Critical patent/JPS5958577A/ja
Publication of JPS6229834B2 publication Critical patent/JPS6229834B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
JP57168925A 1982-09-28 1982-09-28 処理要求中継方式 Granted JPS5958577A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57168925A JPS5958577A (ja) 1982-09-28 1982-09-28 処理要求中継方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57168925A JPS5958577A (ja) 1982-09-28 1982-09-28 処理要求中継方式

Publications (2)

Publication Number Publication Date
JPS5958577A JPS5958577A (ja) 1984-04-04
JPS6229834B2 true JPS6229834B2 (enrdf_load_html_response) 1987-06-29

Family

ID=15877086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57168925A Granted JPS5958577A (ja) 1982-09-28 1982-09-28 処理要求中継方式

Country Status (1)

Country Link
JP (1) JPS5958577A (enrdf_load_html_response)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007166154A (ja) * 2005-12-13 2007-06-28 Nippon Telegr & Teleph Corp <Ntt> 攻撃検出装置、攻撃検出方法および攻撃検出プログラム

Also Published As

Publication number Publication date
JPS5958577A (ja) 1984-04-04

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