JPS62291580A - Test circuit - Google Patents
Test circuitInfo
- Publication number
- JPS62291580A JPS62291580A JP61136690A JP13669086A JPS62291580A JP S62291580 A JPS62291580 A JP S62291580A JP 61136690 A JP61136690 A JP 61136690A JP 13669086 A JP13669086 A JP 13669086A JP S62291580 A JPS62291580 A JP S62291580A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- oscillator
- test
- input
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims 1
- 230000010355 oscillation Effects 0.000 abstract description 12
- 239000003990 capacitor Substances 0.000 abstract description 4
- 235000002597 Solanum melongena Nutrition 0.000 description 4
- 244000061458 Solanum melongena Species 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
発明の詳細な説明
［産業上の利用分野〕
本発明はテス）−回路に関し、特にＣＲ発振器内蔵型の
ＬＳＩのラス１−回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test circuit, and more particularly to an LSI circuit having a built-in CR oscillator.
従来、この種のテスト回路は、ＣＲ発振器の出力端子を
設けてその出力端子から直接発振周波数の測定を行って
いた。Conventionally, this type of test circuit has been provided with an output terminal of a CR oscillator, and the oscillation frequency has been directly measured from the output terminal.
又、最近のＩＣの高密度化の為にＬＳＩのピン数を削減
する傾向にあり、発振周波数の出力ビンを削除したＬＳ
Ｉでは、ＬＳＩの出力端子の波形から発振周波数の算出
を行ったり、一つの目安としてＣＲ発振器の抵抗の値か
ら希望する周波数になっているかの判断を行っていた。In addition, due to the recent trend toward higher density ICs, the number of pins on LSIs has been reduced, and LSIs that have removed the oscillation frequency output bin
In I, the oscillation frequency was calculated from the waveform of the output terminal of the LSI, and as a guide, it was determined whether the desired frequency was obtained from the resistance value of the CR oscillator.
上述した従来のナス１〜回路は、前者の場合はビン数が
増加し後者の場合は発振周波数を間接的にしか測定でき
ず、又、抵抗の値を確認してもコンデンサの値を確める
方法がないので発振周波数の確認がむつかしいという問
題点がある。In the conventional eggplant circuit described above, the number of bins increases in the former case, and in the latter case, the oscillation frequency can only be measured indirectly, and even if the resistance value is checked, the capacitor value cannot be confirmed. The problem is that it is difficult to confirm the oscillation frequency because there is no way to determine the oscillation frequency.
本発明の目的は、°ピン数を増加せずかつ正確に発振周
波数の測定ができるナス１〜回路を提供することにある
。An object of the present invention is to provide a circuit that can accurately measure the oscillation frequency without increasing the number of pins.
ｒ問題点を解決するための手段〕
本発明のナス１〜回路は、ＬＳＩに内蔵されるＣＲ発振
器と、前記ＬＳＩをテスｌ〜状態にするが動作状態にす
るかの制御を行うテスＩ・信号を入力するテスト端子と
、前記ナス１〜状態のとき外部からのクロ７クを入力し
前記動作状態のとき前記ＣＲ発振器の出力信号を出力す
る入出力端子と、前記ナス１〜信号によって開閉制御さ
れ前記ＣＲ発振器の入力端と出力端とを＋ｉ？ｆ記入出
力端子に切換え接続する切換回路とを片んで構成される
。Means for Solving Problems] The eggplant circuit of the present invention includes a CR oscillator built into an LSI, and a test I circuit that controls whether the LSI is brought into the test state or into the operating state. A test terminal that inputs a signal, an input/output terminal that inputs an external clock when in the above-mentioned eggplant 1~ state and outputs the output signal of the CR oscillator when it is in the operation state, and an input/output terminal that opens and closes according to the eggplant 1~ signal. The input terminal and output terminal of the CR oscillator are controlled to +i? f and a switching circuit that is switched and connected to the input/output terminal.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
第１ｒＡにおいて、コンデンサ３と抵抗４とインバータ
５〜９はＣＲ発振器】３を構成している。In the first rA, a capacitor 3, a resistor 4, and inverters 5 to 9 constitute a CR oscillator 3.
なお、インバータ８及び９は負荷がＣＲ発振器内部にＨ
ｇを与えないための増幅素子である。Note that inverters 8 and 9 have a load of H inside the CR oscillator.
This is an amplification element for not giving g.
ＣＲ発振３１３の入力端としての節点１４は１〜ランス
フア１１の一方の端子に接続され、トランスファ１１の
他方の端子は入出力端子ＰＧに接続される。又、Ｃ１”
（発振器１３の出力端１５は１〜ランスフア１２の一方
の端子に接続され、トランスファ１２の他方の端子は入
出力端子ＰＧに接続される。Node 14 as an input terminal of CR oscillation 313 is connected to one terminal of transfer 11 to transfer 11, and the other terminal of transfer 11 is connected to input/output terminal PG. Also, C1”
(The output terminal 15 of the oscillator 13 is connected to one terminal of the transfer wire 1 to 12, and the other terminal of the transfer 12 is connected to the input/output terminal PG.
又、Ｉ・ランスファ１１の制御端子はテスト端子Ｔに接
続され、トランスファ１２の制御端子はインバータ１０
を介してテスｌ〜端子Ｔに接続される。Further, the control terminal of the I transfer 11 is connected to the test terminal T, and the control terminal of the transfer 12 is connected to the inverter 10.
It is connected to the terminal T through the terminal T.
トランスファ１１及び１２とインバータ１０とは切換回
路を構成する。Transfers 11 and 12 and inverter 10 constitute a switching circuit.
テスト端子］゛からのテスト信号が低電位の時、即ちＬ
ＳＩが動乍状態では、トランスファ１２が導通しＩ・ラ
ンスファ１１が非導通となり、入出力端子ＰＧにＣＲ発
振器１３の出力信号が出力されるので、発振周波数のａ
ｍ定ができる。When the test signal from test terminal] is at low potential, that is, L
When SI is in a non-operating state, the transfer 12 is conductive and the I/transfer 11 is non-conductive, and the output signal of the CR oscillator 13 is output to the input/output terminal PG, so that the oscillation frequency a
m-determination is possible.
テスト信号が高電位の時、即ちテスト状悪では、トラン
スファ１１が導通し１〜ランスフア１２が非導通となり
、入出力端子Ｐ Ｇに外部がらＬＳＩテスタのクロック
を入力できる。When the test signal is at a high potential, that is, when the test condition is bad, the transfer 11 becomes conductive and the transfers 1 to 12 become non-conductive, and the clock of the LSI tester can be externally input to the input/output terminal PG.
以上説明したように本発明のテスト回路は、入出力端子
ｔＬｓ Ｉの動作時にはＣＲ発振器の出力端子とし、ナ
ス１〜時には外部からのクロック入力端子として切換え
使用することにより、ＬＳＩのピン数３減少することが
できかつ発振周波数を直接測定できるという効果がある
。As explained above, the test circuit of the present invention reduces the number of LSI pins by 3 by using the input/output terminal tLsI as the output terminal of the CR oscillator when it is in operation, and as the external clock input terminal when the input/output terminal tLsI is in operation. This has the advantage of being able to directly measure the oscillation frequency.
第１図は本発明の一実施例のブロック図である。
３・・・コンデンサ、・４・・・抵抗、５〜１０・・・
インバータ、１１．１２・・Ｉヘランスファ、１３・・
・ＣＲ発振器、ＰＧ・・入出力端子、Ｔ・・・デスｌ一
端子。
５〜ｆＯインハ゛−り、グｆ、ｆ２Ｉ−ランヌファ７３
ＣＦ？、倉振−器
麹ち Ｊ ｒ口FIG. 1 is a block diagram of one embodiment of the present invention. 3... Capacitor, 4... Resistor, 5-10...
Inverter, 11.12... I-heransfa, 13...
・CR oscillator, PG...input/output terminal, T...Desl terminal. 5-fO in-high, gf, f2I-runuper 73
CF? ,Kurashin-Kojichi Jr mouth
Claims (1)
状態にするか動作状態にするかの制御を行うテスト信号
を入力するテスト端子と、前記テスト状態のとき外部か
らのクロックを入力し前記動作状態のとき前記ＣＲ発振
器の出力信号を出力する入出力端子と、前記テスト信号
によって開閉制御され前記ＣＲ発振器の入力端と出力端
とを前記入出力端子に切換え接続する切換回路とを含む
ことを特徴とするテスト回路。A CR oscillator built into the LSI, a test terminal for inputting a test signal for controlling whether the LSI is in a test state or an operating state, and a test terminal for inputting an external clock when in the test state to control the operating state. The method is characterized by comprising an input/output terminal that outputs an output signal of the CR oscillator when , and a switching circuit that is controlled to open and close by the test signal and switches and connects the input end and output end of the CR oscillator to the input/output terminal. test circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136690A JPH0695128B2 (en) | 1986-06-11 | 1986-06-11 | Test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136690A JPH0695128B2 (en) | 1986-06-11 | 1986-06-11 | Test circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62291580A true JPS62291580A (en) | 1987-12-18 |
| JPH0695128B2 JPH0695128B2 (en) | 1994-11-24 |
Family
ID=15181192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61136690A Expired - Lifetime JPH0695128B2 (en) | 1986-06-11 | 1986-06-11 | Test circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0695128B2 (en) |
-
1986
- 1986-06-11 JP JP61136690A patent/JPH0695128B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0695128B2 (en) | 1994-11-24 |
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