JPS62290128A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form stable wiring structure even by a heating process at a high temperature without increasing the resistance of a substrate and a metallic layer by providing a process in which at least one of an silicide film and a nitride film is irradiated with an energy beam. CONSTITUTION:A TiN film 15 constituting a metallic wiring is applied onto the whole surface of l TiSi2 film 14, and the TiSi2 film 14 and the TiN film 15 are formed to a desired pattern. Annealing treat ment in which the patterns of the TiSi2 film 14 and the TiN film 15 shaped onto an oxide film 12 are scanned from the end sections of the patterns by an electron beam 16 set between the TiSi2 film 14 and the TiN film 15 in a maximally heated section by electron injection and the grain size of the TiSi2 film 14 and the TiN film 15 is increased is executed. The crystal grain size of the TiSi2 film 14a and the TiN film 15a grows, and crystal boundary density is reduced. A film such as a tungsten film 17 is applied onto the TiN film 15a, crystal grain size of which is augmented, as the wiring layer of a film consisting of a metal, and a resist is applied and patterned. In such a process, the tungsten film 17 is not changed into an silicide at all, and resistance can be lowered.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, which improves the formation of electrodes or wiring. The present invention relates to a method for manufacturing a device.

(Conventional technology) In recent years, with the increase in the density of semiconductor integrated circuits, wiring resistance,
There is a need to reduce contact resistance between interconnects, contact resistance between interconnects and substrates, etc.

1. For example, it is possible to route semiconductor wiring as a resistor in the upper layer, or to create a high resistance load type memory cell (static
) has become important in C-MO8 circuits and the like.

On the other hand, as a wiring material, for example, a high melting point metal is considered to be promising as a gold maple wiring which is thermally stable and has low electrical resistance. In particular, to reduce wiring resistance,
It is effective to use high melting point metal for wiring. However, even tungsten, which is said to have the highest reaction temperature with silicon among these high-melting point metals, has a temperature of 700°C (700°C).
By passing through the above heating regime, a silicide reaction with the silicon substrate etc. easily occurs.

wife! As shown in FIG.
After forming a diffusion layer (51) by implanting ions such as S, silicon oxide (SiO7) is applied to the entire surface of the silicon aFZ (50) and the diffusion layer (51) using the well-known LPCVD method.
A film (52) is deposited. This oxide film (52) is formed with a connecting hole (53) by ordinary photolithography and IE technology.
) is opened on the diffusion layer (51), and this connection hole (53
) using the LPCVD method to produce high melting point metal tungsten (
Embed Shu, tongue 2. The ten layer (54) is completely formed.

After that, 1 (55) is formed using gold such as aluminum or tungsten on the tungsten layer (s4), patterned, and PSG is formed on this wiring (55).
After the passivation film (5G) was attempted and surpassed ()5
Planarize by baking at a temperature of 0°C to 1050°C for about 30 minutes, or heat the phosphorus during PSGI restoration to 900°C.
During the gelling process at the above temperature, the tungsten (54) and the silicon substrate (50) are turned into silicide through these thermal steps. By forming this silicided tungsten liS, a connection hole (53) is formed.
It is extremely difficult to fill it with tungsten Q (54).

That is, as shown in FIG.
), creating a cavity (58), and it is impossible to make good contact between the diffusion layer (51) and the wiring (55).

In general, even if a thermal process of about 900°C is performed, for example, wiring formed on a silicon substrate and made of a high melting point metal such as tungsten is converted into a silicide during the thermal process, which reduces the resistance of the wiring. Problem 7j, such as increase by one digit or more
l Ah.

As a wiring structure that should overcome such problems, the inventors previously proposed a high melting point structure that exhibits good resistive contact with silicon between the tungsten 1- (53a) and the silicon substrate (50) as shown in FIG. TiSi as a metal alloy.

A film (59) is formed on the silicon substrate (50), and this T
The reaction temperature with silicon on the iS transfusion membrane (59) is 900 °C.
For example, a TiN film (
60) t-intervening membrane (TiSi, film (59),
A structure is proposed in which the TiN film (60) is used as a barrier metal. This barrier metal can suppress silicide from being buried without impairing resistance. Here the 6th
Components that are the same as those in the figure are designated by the same reference numerals and dimensions.

In this structure, compared to a structure in which tungsten and silicon are directly connected, the rate at which tungsten is silicified can be suppressed by about two orders of magnitude when the same thermal process as mentioned above is carried out. However, in this case as well, depending on the time of the thermal process, the tungsten film (5
The silicon atoms reaching the tungsten layer (5)
Silicides (3a) are formed, making it difficult to achieve low resistance. The reason why silicification occurs is as follows. In the process of the thermal process, the TiSi film (59) and the TiN film (59) are formed.
The crystal grain size of 7) naturally increases to about 500A, making it difficult for silicification to occur, but with a grain size of this size, silicon in the silicon substrate (50) will diffuse into the tungsten layer (53a, 1). This is because it is thought that it will become the ninth route.

(Problems to be Solved by the Invention) As described above, the present invention provides a method for manufacturing a semiconductor device in which a high melting point metal or the like is formed on a semiconductor substrate such as silicon through a silicide film and a nitride film of a high melting point metal. When the gold 1,1 passes through a high-temperature thermal process, it reacts with the substrate and causes problems such as silicification, and good contact cannot be made between the substrate and the gold 4 layer, which is a high melting point metal. The present invention solves problems such as the lack of resistance, and realizes a method of forming a stable wiring groove structure even in a high-temperature thermal process without increasing the resistance between the substrate and the metal 1.

[Structure of the invention]

(Measures to Solve the Problems) In order to solve the above problems, the present invention provides an opening on a semiconductor substrate, forms an insulating film, and at least covers the opening with a silicide film of a high melting point metal. A method for manufacturing a semiconductor device in which the silicide film is coated with a nitride film formed on the silicide film, and then a metal film is formed on the nitride film and a post-heating process is performed. According to the present invention, at least one of a silicide film and a nitride film of a high melting point metal formed on a semiconductor substrate such as silicon is provided. By irradiating the crystal with an energy beam, the crystal grain size of this film is increased, that is, the grain boundary density is decreased, so that silicon atoms, etc. of the substrate are irradiated with a high melting point silicide film and a nitride film. It is formed in the gold 1iJSN/J, which is a high-melting point metal, and then diffused into the gold 1iJSN/J, which is a high-melting point metal, during a subsequent thermal process.Because the path is reduced, problems such as silicification of metal films such as high-melting point metals are greatly reduced, and the interconnection itself is It is possible to achieve low resistance.

(Example〕 DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to all the drawings.

FIG. 1 is a ninth step cross-sectional view illustrating all the steps of a semiconductor device manufacturing method according to an embodiment of the present invention.

As shown in FIG.
The diffusion layer (1υ) is crushed by heat treatment at 0°C for 30 minutes. After applying a resist (recess shown in the figure) on this carbonized film, the resist is masked and reactive ion etching (RIH) is performed to form the desired III *The contact hole (13) is connected to the center hole (13) on the diffusion layer 01) f! : After formation, the oxide film ([?] may be used as a mask.

Next, after removing the resist (not shown), the first
As shown in Figure (b), at least the TiSi film (14) constituting the metal wiring is deposited on the diffusion layer (1υ) to a thickness of about 50 OA by simultaneous sputtering.Here, (C,
Contact hole (13) and acid fhim (12) upper V
CmoT! S'*U (14) Ire formation salel. In the careful simultaneous sputtering of Ti5i1 film (14), silicon (S) and titanium (Ti) are irradiated with heavy charged particles such as Ar+ ions onto a target with a certain surface scrap ratio distribution. Next, this Ti
After depositing a TiN film (15) with a film thickness of about 1000A by chemical sputtering on the entire surface of the Si film (14), which also forms a metal interconnection f1, TiSi is formed.

The film (14) and T i NN (15) are formed into a desired pattern using well-known etching techniques.

Sputtering of the TiN film (15) is carried out using a titanium (T1) target in a nitrogen gas atmosphere, for example, Ar+
A silicide film and a nitride film of titanium (Ti) and silicide (Hf), which are formed by ion irradiation, may also be used.

After that, as shown in FIG.
The highest heating part due to α particle injection of μmφ is T
Nine electron beams (16) are set between the iSi film (14) and the TiN film (15) and formed on the oxide film (2).

TiSi was scanned from the pattern end of the film (14) and TiN@(15) in the direction of the arrow in the figure at a scanning speed of 10 cm/sec.

In this example, an annealing (heating) treatment is performed to increase the grain size of the film (14) and the TiN film (15).

Ti8i on oxide film ([2), film (litter) and TiN film (
15) A TiS implanted film (1) is formed at the bottom 1ffi of the contact hole (t3) by annealing from the end of the pattern.
4) and the TiN film (15) may be irradiated with 116 rays.

In other words, considering that the problem of silicification of the wiring layer that is formed afterwards occurs at the bottom of the contact hole ([3), which generally has many contact areas with the silicon substrate (10), the contact hole ([3] Bottom L111] fi
5(') T I S +1 membrane (14), 'J:
' iNM (t!5) FC Heat 1- 'j Just by irradiating it, the effect of completely suppressing silicide formation can be obtained. or,
The Ti8i film (14) and the TiN film (+5) with the oxide film are also irradiated with the electron beam (16).ii:, the A2 film (14).

The effect of (15) in terms of promoting lower resistance can be obtained.

Furthermore, annealing with an electron beam reduces the beam 0) power.
l"iSi!lkan (14) and l' i Nil (15
) The crystal grain size of the film may be increased to match either of the above, but not both.

In this process, 'l' is shown in single figure ((1)).
i.

1% (14a), the crystal grain size of the TiN film (tSa) changes from 10 to 50A immediately after deposition to 5000 to 100A.
It grew to OOA.

Accordingly, the grain boundary density of the unit length is 5XIO
It decreases by more than two orders of magnitude from XIO' lines/cm to 1 to 2 x 104 lines/cm.

Thereafter, as shown in FIG. 1 (fe), the crystal grain size is increased, and a tungsten film (17), for example, is formed by LPCV as a wiring layer of a metal film on the fcT i N film (15a).
After forming a film with a thickness of about 1000 Å using the D method, a resist is applied and patterning is performed. Here, before patterning the Kungesten film (17), the oxide film ([2]
It is also possible to reduce the resistance by irradiating the tungsten film (17) formed above with an electron beam. Mfl mentions TiS i! [(14), 'I' 1NIIIi
The tungsten ffi (17) may be a molybdenum film, an alloy film of these, or an alloy film mainly composed of aluminum. Alternatively, a metal film containing an impurity such as silicon may be used.

Furthermore, a BPSG film (i.e., boron-containing phosphorus) is applied as a protective film on the patterned tungsten film (17).
S GflI8) (18) kcVD method approx. 7000
ArDN.

In such a process, the film is coated with a 3-layer film and then reflowed at 950° C. for 30 minutes to flatten it (see Fig. 1).

No silicide of tungsten fee (17) was observed at all.

We were able to lower the sheet resistance from 120Ω/hole to 0.7Ω/hole than before.

Further, the electron beam annealing step 1-1: or the laser beam annealing step may be substituted.

In the laser beam annealing process, the argon ion laser beam was used with a beam diameter of 50 μmφ and a laser power of 1 to 5 W (
Laser power density 4×104~2×1OsW/cm”
), TiSi, film (14) and TiN film (15) by scanning at a scanning speed of 10 crn/sec.
Or.

Either one of these films (14) and (1!5) can be grown to a grain size f of 5000 to 100OOAK.

Further, the electron beam annealing process can be replaced with a lamp heating process. In this lamp heating step, TiSi, film (14) and TiN film (15) are heated by infrared rays at 1200°C for about 30 seconds in an inert atmosphere such as nitrogen (N) or argon (Ar). It is possible to grow the crystal grain size to 5,000 to 100 OOA.

As mentioned above, regardless of the electron beam, laser beam, or lamp heating method, the irradiation time of the energy beam to the high melting point metal silicide or nitride is short, so the junction depth of the diffusion layer (11) does not increase, and There is no decrease in surface concentration.

FIG. 2 is a cross-sectional view showing an example of the snake of the above embodiment. Components that are the same as those in FIG. 1 are designated by the same reference numerals, and detailed explanations will be omitted.

That is, a 7yTiSi film (14a) and an 'f' i N film (15a) are formed by increasing the crystal grain size in the same manner as in the above-mentioned embodiment, and approximately
After a tungsten film (17) of 000A is deposited to form a wiring pattern, a PSG film, for example, is deposited as an interlayer insulating film (2) on the wiring pattern by LPCVD. Bake at 950°C to 1050°C for about 30 minutes to flatten the surface.

After that, contact was made with the wiring pattern (21
) is filled with tungsten using an LPCVD method, and then a tungsten layer (22) is formed using an etch-back method. For example, aluminum is formed as a wiring film (23) on the tungsten-filled through hole (21) by vapor deposition or the like. In this case, even in the thermal process of psoH baking, the number of silicon groups (10) and tungsten 1
Curve (22) shows that the grain size is increased and the 2TiSi film (,
14a,) and the TiN film (15a), the tungsten layer (, 22) after heat treatment is
) or the expansion layer (1υ) due to the reaction between the tungsten layer (22) and the silicon substrate (10), no PN junction breakdown was observed and a good contact resistance could be obtained. That is, the wiring resistance was 2Ω/ It's less than a mouthful and silicon l'!
The contact resistance with (22) is also the impurity concentration I
cm-”, 1×lXl0'Ω for P type
cm! Below, for N type, it was less than 1×10″Ωcm″. The PSG film (20) may be a ViB PSG film.

FIG. 3 is a final process sectional view showing the second application example. Components that are the same as those in Figure 1 are indicated with the same reference numerals.
Detailed explanation will be omitted.

In other words, in Figure 3, in exactly the same way as in the first application example,
By increasing the grain boundaries by electron beam irradiation, TiSi
! After forming a film (14a) and a TiN film (15a) and depositing a PSG film (20) thereon, the oxide film (20) on the diffusion layer (1υ) is selectively etched to form a contact hole ( Form this contact hole (13a)e.
A tungsten layer (22a) is formed on the tungsten It1 (22a), and then an aluminum wiring (23) is formed as a metal layer on this tungsten It1 (22a) by vapor deposition.

Here, in addition to the case where there is a thermal process of baking the PSG film (20) as in Figure @2, the present invention also applies when a diffusion layer is formed instead of the aluminum wiring (23) on the tungsten layer (22a). That is, a TiN film and a Ti5i layer are deposited in this order on the tungsten layer (22a) in the same manner as in the embodiment described above.

A TiN film is formed by irradiating an energy beam such as an electron beam.
Increases the crystal grain size of TiSi. After that,
A silicon layer is deposited on the entire surface of these films using the LPCVD method.
As ions are implanted into the silicon 14 formed on the tungsten layer (22a) at *t+, 900'C,
Heat treatment is carried out for 30 minutes. In this case as well, a good concrete is obtained without silicification of the tungsten layers (22a, 1), as in the case of the above-mentioned process.

Components that are the same as those in FIG. 2 are designated by the same reference numerals, and detailed explanations will be omitted.

FIG. 4 is a sectional view showing another embodiment of the present invention.

That is, an njM silicon substrate (1
After forming a p+ diffusion 4 (25) by ion-implanting p+ as a mask, the oxide film (24) and the diffusion 78 (25) Approximately 3000 above
Coat with a film thickness of ~4000A. Thereafter, in exactly the same way as in Example 1, a Ti5il film (26) 7) whose crystal grain size was increased by irradiation with a proton beam was deposited on this polysilicon layer (26)7).
14a) After forming the rIN (15a), the fcNi insulating film (20) is selectively etched to form a through hole (21) in the same manner as in the first application example. The through hole (21) is filled with tungsten to form a tungsten layer (22), and the TiN film (+58) and aluminum are formed by @ deposition etc. through this layer (22) to form a total of 10,000 layers (10,000 layers) as wiring. 23) For example, a PSG film or a PSG film is used as an interlayer insulating film in this step.

When a BPSG film is used, after the film is formed, phosphorus gettering is usually performed to remove the phosphorus fF5 contained in the film. In this gettering, 900℃
Although the above thermal process is performed, similar effects can be obtained in this case as well.

The present invention is not limited to the above-mentioned mJ embodiment, but may be used in a furnace with various modifications as appropriate within the range of ξ without departing from the gist of the present invention.

〔Effect of the invention〕

As stated above, according to the present invention, metal wiring made of melting point metal or the like formed on a semiconductor substrate can obtain good contact characteristics without becoming silicified even after undergoing a high-temperature process.

[Brief explanation of drawings]

Fig. 1 is a process sectional view showing one embodiment of the present invention;
Figures 4 to 4 are cross-sectional views for explaining other embodiments of the present invention, and Figures 5 and 6 are t-th cross-sectional views for explaining conventional examples. 10...Silicon substrate, 14+14a...T18i
! film. 15, 15 a-TiN beam, 16-ni beam,
17...Tungsten layer, 18...BP8GBa,
22... Tungsten layer, 23... Interlayer IF9. Figure 1 Figure 1 Figure 1 Figure 2 Figure 3 S Figure 4

Claims (12)

[Claims] (1) Forming an insulating film with an opening on the semiconductor substrate,
A method for manufacturing a semiconductor device, comprising covering at least the opening with a silicide film of a high-melting point metal and a nitride film formed on the silicide film, and then forming a film made of metal on the nitride film, followed by a thermal process. A method of manufacturing a semiconductor device comprising the step of irradiating at least one of the silicide film and the nitride film with an energy beam. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the film made of metal is a wiring or an electrode. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the film made of metal is a high melting point metal or its alloy film, or an alloy film containing aluminum as a main component. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the crystal grain size of the silicide film, the nitride film, or both films is increased to approximately 1000 Å or more by heating with the energy beam. (5) The method for manufacturing a semiconductor device according to claim 1, wherein the energy beam is any one of an electron beam, a laser beam, and xenon lamp light. (6) The method of manufacturing a semiconductor device according to claim 1, wherein the high melting point metal constituting the silicide film and the nitride film is titanium, zirconium, or hafnium. (7) A silicide film or a nitride film of a high melting point metal formed in the opening, or both films are formed continuously up to an insulating film. A method for manufacturing a semiconductor device. (8) The method of manufacturing a semiconductor device according to claim 7, wherein an energy beam is irradiated onto the continuously formed silicide film or nitride film of a high melting point metal, or both films. (9) The method for manufacturing a semiconductor device according to claim 1, wherein the thermal step is a step at 600° C. or higher. (10) The method of manufacturing a semiconductor device according to claim 1, wherein the thermal step is an alloy film sintering step. (11) The method of manufacturing a semiconductor device according to claim 9, wherein the thermal step is a step of baking a passivation film covering a film made of metal. (12) The method for manufacturing a semiconductor device according to claim 11, wherein the passivation film is a PSG or BPSG film.