JPH02151060A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02151060A JPH02151060A JP63304153A JP30415388A JPH02151060A JP H02151060 A JPH02151060 A JP H02151060A JP 63304153 A JP63304153 A JP 63304153A JP 30415388 A JP30415388 A JP 30415388A JP H02151060 A JPH02151060 A JP H02151060A
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- tungsten
- semiconductor device
- insulating film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 52
- 239000010937 tungsten Substances 0.000 claims abstract description 47
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 238000003860 storage Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000010936 titanium Chemical group 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052715 tantalum Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 229910052758 niobium Inorganic materials 0.000 claims description 8
- 239000010955 niobium Substances 0.000 claims description 8
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- -1 yttribium Substances 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical group [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 7
- 229910052735 hafnium Inorganic materials 0.000 claims description 7
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical group [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 7
- 239000011733 molybdenum Chemical group 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 229910052726 zirconium Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000006467 substitution reaction Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 20
- 229910021332 silicide Inorganic materials 0.000 claims 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 230000005669 field effect Effects 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 239000011261 inert gas Substances 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 230000000737 periodic effect Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 229910052723 transition metal Inorganic materials 0.000 claims 1
- 150000003624 transition metals Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 48
- 239000011229 interlayer Substances 0.000 abstract description 19
- 238000009792 diffusion process Methods 0.000 abstract description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005546 reactive sputtering Methods 0.000 abstract description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 abstract description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 abstract description 2
- 229910004481 Ta2O3 Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 3
- 150000003657 tungsten Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Abstract
Description
【産業上の利用分野１
本発明は高集積メモリ素子に係り、特に高容量の蓄積容
量部の構造、製造方法に関する。
【従来の技術】
特開昭５９−２７２９０３に記載の従来技術において、
高誘電率膜の下部電極としてタングステンを用いること
が示されている。
τ発明が解決しようとする課題】
上記の従来技術においては、半導体基体上の凹部を形成
した後、凹部の内表面を含むＳｉ表面に選択的にタング
ステンを成長させた後、キャパシタ絶縁膜を形成し、タ
ングステンを下部電極としていた。
しかし１層間絶縁層を開口して下部基体と導通をとりな
がら、開口部上にキャパシタを形成する場合には、上記
の方法を適用することはできない。
ＣＶＤにより形成されたタングステンはカバレージが悪
く、アスペクト比の大きい導通孔においては導通孔内に
空洞ができてしまう。
本発明の目的は、第１図に概略断面構造を示すようなダ
イナミックメモリの代表的な構造である積層容量型メモ
リセルの様な素子構造において、極めて高容量のキャパ
シタを実現できる容量部の構造および製造方法を提供す
ることにある。INDUSTRIAL APPLICATION FIELD 1 The present invention relates to highly integrated memory devices, and more particularly to the structure and manufacturing method of a high-capacity storage capacitor section. [Prior Art] In the prior art described in Japanese Patent Application Laid-Open No. 59-272903,
It has been shown that tungsten is used as the lower electrode of a high dielectric constant film. τProblem to be Solved by the Invention In the above conventional technology, after forming a recess on a semiconductor substrate, tungsten is selectively grown on the Si surface including the inner surface of the recess, and then a capacitor insulating film is formed. The lower electrode was made of tungsten. However, the above method cannot be applied when forming a capacitor on the opening while establishing conduction with the lower substrate by opening one interlayer insulating layer. Tungsten formed by CVD has poor coverage, and cavities are formed in the through holes with a large aspect ratio. An object of the present invention is to provide a capacitor structure that can realize an extremely high capacitor in an element structure such as a stacked capacitive memory cell, which is a typical dynamic memory structure as shown in the schematic cross-sectional structure of FIG. and to provide a manufacturing method.
この目的を実現するため、本発明においては眉間絶縁層
を開口して半導体基板上の高濃度拡散領域との接続をと
るため、多結晶シリコン層を被着し、この多結晶シリコ
ン層を加工して都ヤパシタの下部電極構造を形成する。
この多結晶シリコン層の表面、もしくは全部をタングス
テンに置換する。このタングステン上に高誘電率の絶縁
膜を形成することで、極めて高容量のキャパシタを形成
することができる。To achieve this purpose, in the present invention, a polycrystalline silicon layer is deposited and this polycrystalline silicon layer is processed in order to open the glabella insulating layer and connect it to the high concentration diffusion region on the semiconductor substrate. to form the lower electrode structure of the capacitor. The surface or the entirety of this polycrystalline silicon layer is replaced with tungsten. By forming an insulating film with a high dielectric constant on this tungsten, a capacitor with extremely high capacity can be formed.
多結晶シリコンをフッ化タングステンにより熱処理する
ことにより、下式に従って多結晶シリコンをタングステ
ンに置換できる。
３Ｓｉ＋２ＷＦ、 ２Ｗ＋３ＳｉＦ４この結果、
少なくともキャパシタの下部電極はタングステンに置換
される。この場合、Ｓｉ表面に薄いＳ ｉ Ｏ，ｌｉを
形成しておくと、１μｍのＳｉもＷに置換される。この
後、ＷＦ、とＳ ｉ Ｈ４とＨ，２，等の反応により、
ＳｉがＷに置換された隙間、あるいは上部にさらにＷを
形成することができるので、キャパシタ絶縁膜を形成す
るＷ表面は十分に滑らかにすることができる。従って、
このタングステン上に例えば、高誘電率のＴａ２０５な
どを絶縁膜とするＭＩＭ型キャパシタを形成することが
でき、ダイナミックメモリ素子の著しい高性能化を実現
することができる。
［実施例］
以下、本発明の一実施例を説明する６
（実施例１）
第１図は本発明の一実施例の半導体装置断面構造を示し
ている。
Ｐ型シリコン（１００）基板１上に素子分離用絶縁膜２
、厚さ１５ｎｍのゲート絶縁膜３．第１層多結晶シリコ
ンゲート４、ソース、トレイン領域となる高濃度拡散層
５．６、ＣＶＤ５ｉＯ，膜からなる層間絶縁膜７を設け
る。その後、直径０゜６μｍのコンタクト孔を介して高
濃度拡散層５に接するように反応性スパッタリングによ
り形成されたバリア金属であるＴｉＮ８とＴｉＮ８と積
層して形成された第２層多結晶シリコンをタングステン
に置換したタングステン層９と、層間絶縁膜１１を形成
してコンタクト孔を介して第２層多結晶シリコンに接し
て形成された第３層多結晶シリコンをタングステンに置
換したタングステン層１２を設ける。さらに、タングス
テン１２の表面を覆う様に形成されたＴａ２０５膜１３
とこのＴａ。
０．１３上に形成されたプレート電極であるタングステ
ン１４が形成されている。
本実施例の半導体装置の蓄積容量は、このタングステン
層１２．１４とＴａ２Ｏ，１３によって形成される。
また、コンタクト孔を介して高濃度拡散層６に接続して
ビット線となるタングステンシリサイド層１ｏが形成さ
れている。タングステン電極１４上に層間路ａ膜１５を
形成し、加工した後、アルミニウム配線層１６を形成し
て、パッシベーション＠１７を被着している。
第２図に示す様に、キャパシタへ印加される電源電圧が
３．３ｖで、１ ／ ２ Ｖ ｃ ｃ方式により絶縁膜
に印加される電圧が主１゜６５Ｖの場合、リフレッシュ
不良に対して十分な信頼性を確保できるリーク電流レベ
ルが１０．’Ａ／ｃｍ”以下であるという条件で、下部
電極を多結晶シリコンからタングステンとすることによ
り容量値は４０％以上増加させることができる。ここで
はプレート電位を任意に設定できると仮定して、耐圧は
キャパシタの両極性の耐圧の平均値として定義した。従
って、この平均値が１，６５Ｖよりも大きいことが条件
となる。
第３図は本発明の半導体装置の製造方法について示す。
Ｐ型シリコン基板１上に素子分離用絶縁膜２゜ゲート絶
縁膜３．第１層多結晶シリコンゲート４、ソース、ドレ
イン領域となる高濃度拡散層５．６、層間絶縁膜７を設
けた後、コンタクト孔を介して高濃度拡散層５に接する
ように形成されたＴｉＮ８と積層して形成された第２層
多結晶シリコン１８を形成し加工した後、層間絶縁膜１
１を形成する。
次に、高濃度拡散層６状にコンタクト孔を開口してビッ
ト線となるタングステンシリサイド１０を形成し、加工
し、層間絶縁膜１２を形成する。
次にコンタクト孔を介して第２層多結晶シリコン１９に
接して形成された３００ｎｍの第３Ｍ多結晶シリコン２
０を形成する。
第１図は第３図に示す半導体基体を、ＷＦ、を用いたＣ
ＶＤ法により、前記多結晶シリコン１９゜２０をタング
ステン膜９．１３に置換した状態を示している。
このＷへの置換に用いたＣＶＤ条件はガス流量Ｗ Ｆ
ｓ ／ Ａ ｒ ＝２０ ／ ２０００ ｓ ｅ ｃ
ｍ ＋全圧力０．５ｔｏｒｒ、温度３５０℃、３０分で
あった。
この後、Ｗ膜の隙間、Ｗの上部表面にＷ［ＩＫを被着、
形成するためにＳｉＨ４とＨ２を加えたＷ−ＣＶＤをさ
らに行った。この場合のＣＶＤ条件はＷＦ、／ＳｉＨ，
／Ｈ２＝１０／１０／２０００ｓｃＣｍ、全圧力０．１
ｔｏｒｒ、デポジション温度は２５０℃、５分であった
。この後、ＬＰＧＶＤ法によりＴａ、○、膜１４を形成
した。ソースは粉末状のＴａＣ１，をＨ２によって昇華
させて８００℃の反応管内に供給し、同時にＮ、Ｏガス
を供給する。
この後、タングステンをＴａ、○、膜上にスパッタ法で
被着し、ドライエツチングにより加工し、プレート電極
１５を形成した。さらに、タングステン１５上に層間絶
縁膜１６となるＣＶＤ−８ｉｏ２膜を形成し、コンタク
トを加工し、次にアルミニウム配線層１７を形成して、
パッシベーション膜１８を形成した。
本実施例ではＳｉをタングステンに置換する例について
示したが、同様にモリブデン、チタニウム、タンタル、
ハフニウム、ジルコニウム、イットリビウム、ニオブに
置換することもできた。これらの金属上に形成されたキ
ャパシタも同様に極めて高容量であり、メモリセルの高
性能化に極めて効果があった。
（実施例２）
第４図は本発明の半導体装置の一例を断面構造を用いて
示している。
Ｐ型シリコン（１００）基板１上に素子分離用絶縁膜２
、厚さ１５ｎｍのゲート絶縁膜３、第１層多結晶シリコ
ンゲート４、ソース、ドレイン領域となる高濃度拡散層
５．６、ＣＶＤＳｉＯ２膜からなる層間絶縁膜７を形成
する。その後、直径０．６μｍのコンタクト孔を介して
高濃度拡散層５に接するように多結晶シリコン層２１、
バリア金属であるＴｉＮ２３を積層して形成する。該Ｔ
ｉＮ上に層間絶縁膜２４を形成してコンタクト孔を介し
てＴｉＮ２１に接して形成された第３層多結晶シリコン
をタングステンに置換したタングステン層２５、タング
ステン２５の表面を覆う様に形成されたＴａ２ｏ５膜１
４とこのＴａ、０Ｓ１４上に形成されたプレート電極で
あるタングステン１５を形成している。
本実施例の半導体装置の蓄積容量はこのタングステン層
２５．１５とＴａ２Ｏ，１４によって形成される。タン
グステン電極１５上に層間絶縁膜１６を形成し、加工し
た後、アルミニウム配線層１７を形成して、パッシベー
ション膜１８を被着している。
本構造でも第１の実施例に示したと同様の製造方法によ
り、タングステン電極ではさまれたＴａ２Ｏ、キャパシ
タが形成される。この場合には、第５図に示す構造を形
成した後、実施例１と同様な方法により第３層多結晶シ
リコン２６をタングステンに置換する。このとき、バリ
ア絶縁膜２３により置換反応は多結晶シリコン２１まで
至らない。
従って、高濃度拡散層の周辺の接合特性が劣化すること
はない。
・本実施例ではＳｉをタングステンに置換する例につい
て示したが、同様にモリブデン、チタニウム、タンタル
、ハフニウム、ジルコニウム、イットリビウム、ニオブ
に置換することもできた。これらの金属上に形成された
キャパシタも同様に極めて高容量であり、メモリセルの
高性能化に極めて効果があった。By heat-treating polycrystalline silicon with tungsten fluoride, polycrystalline silicon can be replaced with tungsten according to the following formula. 3Si+2WF, 2W+3SiF4 As a result,
At least the lower electrode of the capacitor is replaced with tungsten. In this case, if a thin layer of SiO,li is formed on the Si surface, 1 μm of Si is also replaced with W. After this, by the reaction of WF, S i H4 and H,2, etc.,
Since W can be further formed in the gap where Si is replaced with W or above, the W surface on which the capacitor insulating film is formed can be made sufficiently smooth. Therefore,
An MIM type capacitor having an insulating film made of, for example, Ta205 having a high dielectric constant can be formed on this tungsten, and a significant improvement in the performance of the dynamic memory element can be realized. [Embodiment] An embodiment of the present invention will be described below.6 (Embodiment 1) Fig. 1 shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. Element isolation insulating film 2 on P-type silicon (100) substrate 1
, 15 nm thick gate insulating film 3. A first layer polycrystalline silicon gate 4, a high concentration diffusion layer 5.6 serving as a source and train region, and an interlayer insulating film 7 made of a CVD 5iO film are provided. Thereafter, a second layer of polycrystalline silicon, which was formed by stacking TiN8 and TiN8, which are barrier metals formed by reactive sputtering, was placed in contact with the highly concentrated diffusion layer 5 through a contact hole with a diameter of 0.6 μm. A tungsten layer 12 is provided in which tungsten is substituted for the third layer polycrystalline silicon formed by forming an interlayer insulating film 11 and in contact with the second layer polycrystalline silicon through a contact hole. Furthermore, a Ta205 film 13 is formed to cover the surface of the tungsten 12.
Toko Ta. Tungsten 14, which is a plate electrode formed on 0.13 mm, is formed. The storage capacitor of the semiconductor device of this embodiment is formed by the tungsten layers 12, 14 and Ta2O, 13. Further, a tungsten silicide layer 1o is formed which is connected to the high concentration diffusion layer 6 through a contact hole and becomes a bit line. After forming and processing an interlayer path a film 15 on the tungsten electrode 14, an aluminum wiring layer 16 is formed and passivation@17 is applied. As shown in Figure 2, when the power supply voltage applied to the capacitor is 3.3V and the voltage applied to the insulating film by the 1/2 Vcc method is mainly 1°65V, it is sufficient to prevent refresh failure. The leakage current level that ensures high reliability is 10. The capacitance value can be increased by more than 40% by changing the lower electrode from polycrystalline silicon to tungsten, provided that the voltage is below 'A/cm'.Here, assuming that the plate potential can be set arbitrarily, The breakdown voltage is defined as the average value of the breakdown voltages of both polarities of the capacitor. Therefore, the condition is that this average value is greater than 1.65 V. Figure 3 shows the method for manufacturing the semiconductor device of the present invention. P type After forming an element isolation insulating film 2, a gate insulating film 3, a first layer polycrystalline silicon gate 4, a high concentration diffusion layer 5, which will become a source and drain region, and an interlayer insulating film 7 on a silicon substrate 1, contacts are formed. After forming and processing a second layer polycrystalline silicon 18 formed by laminating TiN 8 formed so as to be in contact with the high concentration diffusion layer 5 through the hole, an interlayer insulating film 1 is formed.
form 1. Next, a contact hole is opened in the shape of the high concentration diffusion layer 6 to form a tungsten silicide 10 which will become a bit line, and is processed to form an interlayer insulating film 12. Next, a 3M polycrystalline silicon 2 of 300 nm is formed in contact with the second layer polycrystalline silicon 19 through the contact hole.
form 0. FIG. 1 shows the semiconductor substrate shown in FIG.
This shows the state in which the polycrystalline silicon 19.degree. 20 is replaced with a tungsten film 9.13 by the VD method. The CVD conditions used for this replacement with W were the gas flow rate W F
s / A r =20 / 2000 s e c
m + total pressure of 0.5 torr, temperature of 350° C., and 30 minutes. After this, W [IK is applied to the gap between the W films and the upper surface of W.
W-CVD with SiH4 and H2 was further performed for formation. The CVD conditions in this case are WF, /SiH,
/H2=10/10/2000scCm, total pressure 0.1
torr, and the deposition temperature was 250° C. for 5 minutes. Thereafter, a Ta film 14 was formed using the LPGVD method. As a source, powdered TaCl is sublimed by H2 and supplied into a reaction tube at 800°C, and at the same time, N and O gases are supplied. Thereafter, tungsten was deposited on the Ta, O, film by sputtering and processed by dry etching to form the plate electrode 15. Furthermore, a CVD-8io2 film that will become an interlayer insulating film 16 is formed on the tungsten 15, contacts are processed, and then an aluminum wiring layer 17 is formed.
A passivation film 18 was formed. This example shows an example in which Si is replaced with tungsten, but similarly molybdenum, titanium, tantalum,
Substitution with hafnium, zirconium, yttribium, and niobium was also possible. Capacitors formed on these metals also had extremely high capacitance and were extremely effective in improving the performance of memory cells. (Example 2) FIG. 4 shows an example of a semiconductor device of the present invention using a cross-sectional structure. Element isolation insulating film 2 on P-type silicon (100) substrate 1
, a gate insulating film 3 with a thickness of 15 nm, a first layer polycrystalline silicon gate 4, a high concentration diffusion layer 5.6 which will become the source and drain regions, and an interlayer insulating film 7 made of a CVDSiO2 film are formed. Thereafter, a polycrystalline silicon layer 21 is placed in contact with the high concentration diffusion layer 5 through a contact hole having a diameter of 0.6 μm.
It is formed by stacking TiN23, which is a barrier metal. The T
An interlayer insulating film 24 is formed on iN, and a third layer formed in contact with TiN 21 through a contact hole is a tungsten layer 25 in which the polycrystalline silicon is replaced with tungsten, and a Ta2O5 layer is formed to cover the surface of the tungsten 25. Membrane 1
4 and this Ta, a tungsten 15 which is a plate electrode formed on the 0S 14 is formed. The storage capacitor of the semiconductor device of this embodiment is formed by this tungsten layer 25.15 and Ta2O, 14. After forming and processing an interlayer insulating film 16 on the tungsten electrode 15, an aluminum wiring layer 17 is formed and a passivation film 18 is deposited thereon. In this structure, a Ta2O capacitor sandwiched between tungsten electrodes is formed by the same manufacturing method as shown in the first embodiment. In this case, after forming the structure shown in FIG. 5, the third layer polycrystalline silicon 26 is replaced with tungsten using the same method as in Example 1. At this time, the substitution reaction does not reach the polycrystalline silicon 21 due to the barrier insulating film 23. Therefore, the bonding characteristics around the high concentration diffusion layer will not deteriorate. - Although this example shows an example in which Si is replaced with tungsten, it is also possible to similarly replace it with molybdenum, titanium, tantalum, hafnium, zirconium, yttribium, or niobium. Capacitors formed on these metals also had extremely high capacitance and were extremely effective in improving the performance of memory cells.
本発明によれば、積層容量型のダイナミックメモリにお
いて従来のプロセスを大きく変更することなく１選択的
に蓄積電極の表面のみをタングステンに置換することが
できる。このため、高誘電率の酸化タンタルなどをキャ
パシタ絶縁膜とする高容量のキャパシタを形成できるの
で、メモリ素子の高集積化、高性能化に極めて効果があ
る。According to the present invention, only the surface of the storage electrode can be selectively replaced with tungsten in a stacked capacitor type dynamic memory without significantly changing the conventional process. Therefore, it is possible to form a high-capacity capacitor using tantalum oxide or the like having a high dielectric constant as the capacitor insulating film, which is extremely effective in increasing the integration and performance of memory elements.
第１図は本発明の一実施例の積層容量型メモリセルの断
面構造模式図、第２図は実施例１において示した半導体
装置の積層容量の耐圧と容量の関係を示す特性図、第３
図は第１図に示す半導体装置の製造途中の断面構造模式
図、第４図は本発明の他の実施例の積層容量型メモリセ
ルの断面構造模式図、第５図は第１図に示す半導体装置
の製造工程の他の一例を示す断面構造模式図である。
符号の説明
１・・・Ｐ型Ｓｉ基板、２・・・分離絶縁膜、３・・・
ゲート絶縁膜、４・・・第１層多結晶シリコンゲート、
５・・・高濃度拡散層、６・・・高濃度拡散層、７・・
・層間絶縁膜、８・・・ＴｉＮ、９・・・タングステン
、１０・・・ビット線、１１・・・層間絶縁膜、１２・
・・層間絶縁膜、１３・・・タングステン、１４・・・
Ｔａ２０５．１５・・・タングステン、１６・・・層間
絶縁膜、１７・・・アルミニウム、１８・・・パッシベ
ーション膜、１９・・・第２層多結晶シリコン、２０・
・・第３層多結晶シリコン、２１・・・第２層多結晶シ
リコン、２２・・・層間絶縁膜。
２３・・・ＴｉＮ、２４・・・層間絶縁膜、２５・・・
タングステン
第２図
第５図
％１図
４Ｊ
／θダ ／
第３図
第４図FIG. 1 is a schematic cross-sectional structure diagram of a laminated capacitor type memory cell according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the relationship between breakdown voltage and capacitance of the laminated capacitor of the semiconductor device shown in Example 1, and FIG.
The figure shows a schematic cross-sectional structure of the semiconductor device shown in FIG. 1 during manufacture, FIG. 4 shows a schematic cross-sectional structure of a stacked capacitive memory cell according to another embodiment of the present invention, and FIG. 5 shows the structure shown in FIG. FIG. 7 is a schematic cross-sectional structure diagram showing another example of the manufacturing process of a semiconductor device. Explanation of symbols 1... P-type Si substrate, 2... Isolation insulating film, 3...
Gate insulating film, 4... first layer polycrystalline silicon gate,
5...High concentration diffusion layer, 6...High concentration diffusion layer, 7...
-Interlayer insulating film, 8...TiN, 9...tungsten, 10...bit line, 11...interlayer insulating film, 12.
...Interlayer insulating film, 13...Tungsten, 14...
Ta205.15...Tungsten, 16...Interlayer insulating film, 17...Aluminum, 18...Passivation film, 19...Second layer polycrystalline silicon, 20...
...Third layer polycrystalline silicon, 21...Second layer polycrystalline silicon, 22...Interlayer insulating film. 23... TiN, 24... Interlayer insulating film, 25...
Tungsten Fig. 2 Fig. 5 % 1 Fig. 4 J /θda / Fig. 3 Fig. 4
Claims (1)
型の二つの領域でソースおよびドレイン領域を構成した
絶縁ゲート型電界効果トランジスタの上記ソースまたは
ドレイン領域に接触し、かつ第１の絶縁膜を介して前記
トランジスタのゲートとなる第１導電物質上に少なくと
もその一部が重なるように第２の導電物質を堆積し、該
第２の導電物質を加工した後、該第２の導電物質の一部
もしくは全てを第３の導電物質に置換し、該第３の導電
物質上に第２の絶縁膜、第４の導電物質を順次堆積し、
前記第３の導電物質、第２の絶縁膜、第４の導電物質に
て記憶容量を構成している半導体装置において、該第３
の導電物質は少なくとも第２の絶縁膜が被着される界面
側がタングステン、モリブデン、チタニウム、タンタル
、ハフニウム、ジルコニウム、イットリビウム、ニオブ
もしくはこれらの元素のシリサイドのいずれかに置換さ
れていることを特徴とする半導体装置。 ２、請求項第１項記載の半導体装置を製造する方法にお
いて、上記第２の導電物質としてシリコン層を基体全面
に被着する工程と、該シリコン層を加工して該記憶容量
の下部電極を形成する工程と、基板表面に露出したシリ
コン層をタングステン、モリブデン、チタニウム、タン
タル、ハフニウム、ジルコニウム、イットリビウム、ニ
オブなどのガス状弗化物あるいは窒素（Ｎ＿２）やアル
ゴン（Ａｒ）などの不活性ガスで希釈した該ガス状弗化
物との置換反応を用いた化学気相成長法により、該シリ
コン層の一部もしくは全てを選択的にタングステン、モ
リブデン、チタニウム、タンタル、ハフニウム、ジルコ
ニウム、イットリビウム、ニオブもしくはこれらの元素
のシリサイドに置換して該第３の導電物質を形成する工
程を有することを特徴とする半導体装置の製造方法。 ３．上記誘電体膜は少なくとも元素周期表の３ａ族、４
ａ族、５ａ族からなる元素の酸化物を含むことを特徴と
する請求項第１項記載の半導体装置。 ４、上記第３の導電物質としてＷ、Ｍｏ、Ｐｔ、Ａｕな
どの金属、もしくはＷ、Ｍｏ、Ｔｉ、Ｔａ、Ａｌなどの
窒化物、あるいはＷ、Ｍｏ、Ｔｉ、Ｔａ、Ｃｏ等のシリ
サイド、およびＴｉＷなどの合金を用いたことを特徴と
する請求項第１項記載の半導体装置。 ５、上記第２の導電物質と上記ソース、ドレイン領域の
界面にバリア膜を形成した後、該第２の導電物質の一部
、もしくはすべてをタングステン、モリブデン、チタニ
ウム、タンタル、ハフニウム、ジルコニウム、イットリ
ビウム、ニオブもしくはこれらの元素のシリサイドに置
換したことを特徴とする請求項第１項記載の半導体装置
。 ６、上記第２の導電物質は該ソース、ドレイン領域上に
形成された第４の導電物質、バリア膜、第５の導電物質
の積層構造からなっていて、該第５の導電物質がタング
ステン、モリブデン、チタニウム、タンタル、ハフニウ
ム、ジルコニウム、イットリビウム、ニオブもしくはこ
れらの元素のシリサイドに置換したことを特徴とする請
求項第１項記載の半導体装置。 ７、上記バリア絶縁膜は遷移金属（Ｗ、Ｍｏ、Ｔｉ、Ｔ
ａ等）、Ｗ、Ｍｏ、Ｔｉ、Ｔａ、Ａｌなどの窒化物、Ｗ
、Ｍｏ、Ｔｉ、Ｔａ、Ｃｏ等のシリサイド、ＴｉＷなど
の合金を用いたことを特徴とする請求項第５項もしくは
６項記載の半導体装置。 ８、上記第２、第５の導電物質は単結晶シリコン、多結
晶シリコン、非晶質シリコン、および不純物を含む前記
シリコンであることを特徴とする請求項第１記載の半導
体装置。[Claims] 1. Contacting the source or drain region of an insulated gate field effect transistor in which the source and drain regions are formed by two regions of a second conductivity type formed on the surface of a semiconductor substrate of a first conductivity type. and depositing a second conductive material so as to at least partially overlap the first conductive material that will become the gate of the transistor via a first insulating film, and processing the second conductive material. , replacing part or all of the second conductive material with a third conductive material, and sequentially depositing a second insulating film and a fourth conductive material on the third conductive material,
In the semiconductor device in which a storage capacity is constituted by the third conductive material, the second insulating film, and the fourth conductive material, the third conductive material
The conductive material is characterized in that at least the interface side on which the second insulating film is deposited is substituted with tungsten, molybdenum, titanium, tantalum, hafnium, zirconium, yttribium, niobium, or a silicide of these elements. semiconductor devices. 2. A method for manufacturing a semiconductor device according to claim 1, including the steps of depositing a silicon layer as the second conductive material over the entire surface of the substrate, and processing the silicon layer to form a lower electrode of the storage capacitor. The silicon layer exposed on the substrate surface is treated with a gaseous fluoride such as tungsten, molybdenum, titanium, tantalum, hafnium, zirconium, yttribium, or niobium, or an inert gas such as nitrogen (N_2) or argon (Ar). Part or all of the silicon layer is selectively coated with tungsten, molybdenum, titanium, tantalum, hafnium, zirconium, yttribium, niobium, or any of these by chemical vapor deposition using a substitution reaction with the diluted gaseous fluoride. A method for manufacturing a semiconductor device, comprising the step of forming the third conductive material by replacing an element with silicide. 3. The dielectric film is at least group 3a and group 4 of the periodic table of elements.
2. The semiconductor device according to claim 1, wherein the semiconductor device contains an oxide of an element belonging to group a or group 5a. 4. The third conductive substance is a metal such as W, Mo, Pt, or Au, or a nitride such as W, Mo, Ti, Ta, or Al, or a silicide such as W, Mo, Ti, Ta, or Co, and 2. The semiconductor device according to claim 1, wherein an alloy such as TiW is used. 5. After forming a barrier film at the interface between the second conductive material and the source and drain regions, part or all of the second conductive material is replaced with tungsten, molybdenum, titanium, tantalum, hafnium, zirconium, or yttribium. 2. The semiconductor device according to claim 1, wherein the semiconductor device is substituted with niobium, niobium, or a silicide of these elements. 6. The second conductive material has a laminated structure of a fourth conductive material formed on the source and drain regions, a barrier film, and a fifth conductive material, and the fifth conductive material is tungsten, 2. The semiconductor device according to claim 1, wherein the semiconductor device is substituted with molybdenum, titanium, tantalum, hafnium, zirconium, yttribium, niobium, or a silicide of these elements. 7. The barrier insulating film is made of transition metals (W, Mo, Ti, T
a), W, Mo, Ti, Ta, Al and other nitrides, W
7. The semiconductor device according to claim 5, wherein a silicide such as Mo, Ti, Ta, or Co, or an alloy such as TiW is used. 8. The semiconductor device according to claim 1, wherein the second and fifth conductive materials are monocrystalline silicon, polycrystalline silicon, amorphous silicon, and the silicon containing impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63304153A JP2796323B2 (en) | 1988-12-02 | 1988-12-02 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63304153A JP2796323B2 (en) | 1988-12-02 | 1988-12-02 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02151060A true JPH02151060A (en) | 1990-06-11 |
| JP2796323B2 JP2796323B2 (en) | 1998-09-10 |
Family
ID=17929694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63304153A Expired - Fee Related JP2796323B2 (en) | 1988-12-02 | 1988-12-02 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2796323B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2667727A1 (en) * | 1990-10-08 | 1992-04-10 | Gold Star Electronics | Device of the dynamic random-access memory type and its method of fabrication in high integrated form |
| JPH04206569A (en) * | 1990-11-30 | 1992-07-28 | Nec Corp | Manufacture of semiconductor device |
| JPH04359557A (en) * | 1991-06-06 | 1992-12-11 | Nec Corp | Method of manufacturing semiconductor device |
| US5336638A (en) * | 1991-03-06 | 1994-08-09 | Hitachi, Ltd. | Process for manufacturing semiconductor devices |
| US5359217A (en) * | 1992-08-11 | 1994-10-25 | Nippon Steel Corporation | MOS semiconductor memory device having stack capacitor with metal plug |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57120295A (en) * | 1981-01-17 | 1982-07-27 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPS60152049A (en) * | 1984-01-20 | 1985-08-10 | Hitachi Ltd | Capacitor |
| JPS6110233A (en) * | 1984-06-02 | 1986-01-17 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS62290128A (en) * | 1986-06-10 | 1987-12-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63250462A (en) * | 1987-04-07 | 1988-10-18 | Ulvac Corp | Formation of thin metallic film |
-
1988
- 1988-12-02 JP JP63304153A patent/JP2796323B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57120295A (en) * | 1981-01-17 | 1982-07-27 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPS60152049A (en) * | 1984-01-20 | 1985-08-10 | Hitachi Ltd | Capacitor |
| JPS6110233A (en) * | 1984-06-02 | 1986-01-17 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS62290128A (en) * | 1986-06-10 | 1987-12-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63250462A (en) * | 1987-04-07 | 1988-10-18 | Ulvac Corp | Formation of thin metallic film |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2667727A1 (en) * | 1990-10-08 | 1992-04-10 | Gold Star Electronics | Device of the dynamic random-access memory type and its method of fabrication in high integrated form |
| JPH04206569A (en) * | 1990-11-30 | 1992-07-28 | Nec Corp | Manufacture of semiconductor device |
| US5336638A (en) * | 1991-03-06 | 1994-08-09 | Hitachi, Ltd. | Process for manufacturing semiconductor devices |
| JPH04359557A (en) * | 1991-06-06 | 1992-12-11 | Nec Corp | Method of manufacturing semiconductor device |
| US5359217A (en) * | 1992-08-11 | 1994-10-25 | Nippon Steel Corporation | MOS semiconductor memory device having stack capacitor with metal plug |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2796323B2 (en) | 1998-09-10 |
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