JPS62288915A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption by providing an ECL semiconductor integrated circuit with two or more power generating circuits whose generation voltages can be controlled with a signal having the same level as the input/ output voltage. CONSTITUTION:An internal circuit 1 of the ECL semiconductor integrated circuit is divided into blocks 1-a, 1-b, 1-c, and 1-d, and power generating circuits 6-1, 6-b, 6-c, and 6-d are connected to respective blocks. Circuits 6-1, 6-b, 6-c, and 6-d are controlled by signals to power generating circuit control terminals 5-a, 5-b, 5-c, and 5-d. In case, for example, a two-stage shift register in the circuit 1 is in a packaged state and it is unnecessary to operate it for a certain time, -0.8V in the ECL high level is inputted to the signal terminal, which controls the power generating circuit from which a constant voltage is supplied to the two-stage shift register, to reduce the switching current in the two-stage shift register, and the power consumption is reduced.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an ECL type semiconductor integrated circuit device, and particularly relates to an ECL type semiconductor integrated circuit device that can reduce power consumption and create a standby state.
type semiconductor integrated circuit device.

[Conventional technology]

Conventionally, an ECL type semiconductor integrated circuit device has been comprised of an internal circuit 7, an output buffer circuit 8, and various power generation circuits 9, as shown in FIG. Switching currents for the internal circuits and input/output buffer circuits were provided by constant current sources using constant voltages supplied from various power generation circuits.

[Problem that the invention seeks to solve]

Since the conventional ECL type semiconductor integrated circuit device described above uses the current generated by the constant voltage source as the switching current, a constant current (jtL) is always flowing through the ECL type semiconductor integrated circuit device. As long as the device is powered on within the device, it will require constant power.

However, in some devices, all the components may not be in operation at all times, and in this case, in conventional 0ECL semiconductor integrated circuit devices, switching current flows even though they are not in operation, resulting in wasted power consumption. There is. Also, in some ECL type semiconductor integrated circuit devices, all the circuits may not be operating at all times, and even in this case,
Conventional ECL semiconductor integrated circuit devices suffer from the disadvantage that switching current flows even though some circuits are not operating, resulting in wasted power consumption.

In contrast to the conventional QECL type semiconductor integrated circuit device described above, the present invention is an original technology that reduces power consumption by controlling the generated voltages of a plurality of internal power generation circuits using signals at the same level as the input/output signal level. It has a certain content.

[Problem't-Means for solving it]

The ECLm semiconductor integrated circuit device of the present invention includes two or more power generation circuits that can control the generated voltage by a signal at the same level as the input/output signal level, and two or more power generation circuits that control the power generation circuit.
It has more than one signal terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows one embodiment of the present invention. 1 is internal circuit, 2
is human power or output buffer circuit, 3 is power supply terminal,
4 is a signal terminal. The internal circuits are 1-a, 1-b, 1
-C, and 1-d are divided into 7 blocks, and the clocks of each internal circuit are 5-a, 5-b, 5.
-c, and 5-d (7) 5-a, 5-b, respectively controlled by a signal to the power generation circuit control signal terminal.
It is connected to the power generation circuits 5-c and 6-d. Next, a power generation circuit that can control the generated voltage based on the input/output signal level will be explained with reference to FIG. The circuit on the left side of the broken line is a power generation circuit called a conventional band gap reference circuit, and the circuit on the right side of the broken line is a circuit that controls the power generation circuit. By inputting the ECL level (-0,8V to -1,6V) to the power generation circuit control terminal 10, the base potential of transistor 1 changes from -3,2V to -46V.
The level is shifted to 0■. When the power supply of transistor 12 is set to -4.5■, the base potential of transistor 1 becomes much lower than the base potential of transistor B and becomes higher than that of transistor B due to the switching of transistor 10, and the collector current IC of transistor 3 flows as follows. Sometimes it doesn't flow. ■. The value when flows ■. =IX10-3A.

! The value when I, does not flow■. , = IX10''A, the voltage fluctuation △■ of the constant voltage output terminal 14 is = 0.
36V (T-300@K). The output constant voltage is applied to a constant voltage application terminal 15 of the current switch shown in FIG. Therefore, the voltage fluctuation Δ■
The difference d in the voltage consumption due to the power supply voltage ■E and the resistance value R of 16 is... (2) As shown above, the voltage generation circuit control of 10 in Fig. 3 Connect the terminal to ECL level @lH” level = -0,8V
By doing so, the power consumption can be reduced by the value indicated by each gate value (2).

An example of the internal circuit of FIG. 1 is shown in FIG. 17 is D-F,
F, , 18 is a clock driver), and the internal circuit is as follows:
Each block is divided into clocks 19-a, 19-b, 19-c, and 19-d, and each block constitutes a 2-stage shift register, a 4-stage shift register, a 6-stage shift register, and a clock driver. 1 in Figure 1
They are arranged at a*1-b, 1-c, and 1-d. When a certain circuit in the ECL type semiconductor integrated circuit device of this embodiment, for example, a two-stage shift register, is mounted and does not need to operate for a certain period of time, the power source that supplies constant voltage to the two-stage shift register EC to the signal terminal that controls the circuit
By changing the "H" level to the "L" level and the 8Vk input f, the switching current in the two-stage shift register can be reduced and power consumption can be reduced.

FIG. 6 shows a second embodiment of the present invention. 20 is an internal circuit, 2
1 is an input or output buffer termination circuit, 22 is a power supply terminal, and 23 is an input/output terminal. The internal circuits are each 20-a
, 20-b and 20-c are divided into blocks, and each internal circuit block Fi valley 24-a, 24-
b, and connected to power generation circuits 24-c and 24-d. The power generation circuit 24-a is connected to the power generation circuit control signal terminal 25-a, 24-b is connected to 25-b, 24-C,
24-d is connected to 25-C. In this embodiment, as in 25-C, one power generation circuit control signal terminal is connected to two power generation circuits, which reduces the number of power generation circuit control signal terminals and reduces power consumption. be able to.

〔Effect of the invention〕

As explained above, the present invention provides an ECL type semiconductor integrated circuit device including two or more power generation circuits that can control the generated voltage by signals having the same level as the input/output signal level;
By having two or more signal terminals that control the power generation circuit, it is possible to control the power generation circuit that supplies constant voltage to circuits that do not operate for a certain period of time, partially reducing switching current and reducing power consumption. There is an effect that it can be done.

[Brief explanation of the drawing]

FIG. 1 shows one embodiment of the present invention, FIG. 2 shows a conventional 0ECL type semiconductor integrated circuit device, and FIG. 3 shows a power generation circuit of one embodiment.
FIG. 4 shows a basic gate circuit of one embodiment, FIG. 5 shows an internal circuit of one embodiment, and FIG. 6 shows a second embodiment. 1... Internal circuit, 2... Input or output buffer, 3... Power supply terminal, 4...
...Input/output terminal, 5...Power generation circuit control terminal, 6...Power generation circuit, 7...Internal circuit, 8...Manual power or output Buffer, 9...
...Power generation circuit, 10...Power generation circuit control signal terminal, 11...Transistor, 12...
...Power supply, 13...Transistor, 14.
... Constant voltage output terminal, 15 ... Constant voltage application terminal, 16 ... Resistor, 17 ... D-FF,
18... Black 9 driver, 19...
Internal circuit proof, 20...Internal circuit, 21.
...Input or output buffer, 22...
Power supply terminal, 23... Input/output terminal, 24...
...Power generation circuit, 25...Power generation circuit control signal terminal. Figure 83 Ward @4 Flash

Claims (1)

[Claims] An ECL type semiconductor integrated circuit characterized by having two or more power generation circuits capable of controlling the generated voltage by signals having the same level as the input/output signal level, and two or more signal terminals for controlling the power generation circuits. ECL type semiconductor integrated circuit.