JPH04288874A - Master slice lsi - Google Patents

Abstract

PURPOSE:To enable an unneeded power consumption to be reduced by providing a switching element between a cell of a master slice LSI and a power supply which drives it. CONSTITUTION:When an input port 1a is at a logic level 0, a logic operation of a block circuit 5 consumes an unneeded power since a logic level of an output port 2 is at the logic level 0. Therefore, when an input port 1a is at the logic level 0, switch elements 7a-7c are turned off by a control circuit 9, the circuit block 5 is turned into non-operation state, thus enabling power which is consumed by the block 5 to be reduced. At this time, a pull-down element 8 is provided to prevent one input terminal 6 of a cell 3d from becoming a logic level 'undefined'. When the input port 1a is at a logic level 1, the logic level of the output port 2 is determined by the logic of the circuit block 5, thus allowing the control circuit 9 to turn on switch elements 7a-7c an the circuit block 5 in operation state.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice LSI that achieves low power consumption.

0002

2. Description of the Related Art FIG. 2 shows an example of a circuit constructed on a conventional master slice LSI. In the figure, 1a, 1b,
1c, 1d are input ports, 2 is output port, 3a, 3
b, 3c, 3d are cells configured using MOS transistors in the master slice LSI; 4a, 4b, 4c, 4
d is a power supply that drives cells 3a, 3b, 3c, and 3d, respectively; 5 is a circuit block that is a part of this circuit; and 6 is an input terminal that serves as an output of circuit block 5 and one input of cell 3d. .

Next, the operation will be explained. Cell 3a, 3
b, 3c, and 3d are power supplies 4a, 4b, 4c, and 4, respectively.
d and is in operation. In this circuit, by applying a voltage corresponding to logic level 0 or 1 to input ports 1a, 1b, 1c, and 1d, the potential of output port 2 changes depending on the functions of cells 3a, 3b, 3c, and 3d. That is, the logic level is determined.

0004

[Problems to be Solved by the Invention] Since the conventional master slice LSI is configured as described above, when one input port has a logic level of 0, the output can be output regardless of the logic level of the other input ports. The logic level of the port is 0, and a change in the logic level of the other input ports causes an unnecessary logic level change in the circuit block, resulting in unnecessary power consumption.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a master slice LSI that can reduce unnecessary power consumption that occurs when an unnecessary change in logic level occurs at an input port. With the goal.

[0006]

[Means for Solving the Problems] A master slice LSI according to the present invention has a switching element between a cell configured using a MOS transistor in the master slice LSI and a power supply for driving the cell, It has a structure that allows connections and disconnections between sectors in a slice LSI and a power supply.

[0007]

[Operation] In the master slice LSI of the present invention, when a cell causes an unnecessary change in logic level and is in a state of consuming unnecessary power, the master slice LSI of the present invention prevents the connection between the cell and the power supply by using a switching element between the cell and the power supply. Connected state to prevent unnecessary power consumption.

[0008]

[Example] Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1a to 1d, 2, 3a
3d, 4a to 4d, 5, and 6 are the same as 1a to 1d, 2, 3a to 3d, 4a to 4d, 5, and 6 shown in the conventional example of FIG. 2, so the explanation will be omitted. 7a, 7b, 7c are cells 3a, 3b, 3c and power supplies 4a, 4b, 4c, respectively.
8 is a switch element using a P-channel transistor provided between the n
A pull-down element 9 using a channel transistor is
This is a control circuit that controls the switch elements 7a to 7c and the pull-down element 8.

Next, the operation will be explained. Input port 1
When a is a logic level 0, in the conventional example shown in FIG. 1, the logic level of the output port 2 is 0 regardless of the input terminal 6, so the logic operation of the block circuit 5 consumes unnecessary power. Therefore, when the input port 1a is at logic level 0, the control circuit 9 controls the switching elements 7a to 7c.
is turned off, the circuit block 5 is rendered inactive, and the power consumed by the block 5 is reduced. At this time, cell 3d
A pull-down element 8 is provided to prevent one input terminal 6 from becoming undefined in logic level.

When the input port 1a is at logic level 1,
Since the logic level of the output port 2 is determined by the logic of the circuit block 5, the control circuit 9 turns on the switch elements 7a to 7c to put the circuit block 5 into an operating state.

Example 2. In the above embodiment, the switch elements 7a to 7c are provided for each of the cells 3a to 3c, but the switch elements 7a to 7c may be implemented by a single element.

Example 3. In addition, although the above embodiment shows an example in which P-channel transistors are used as the switch elements 7a to 7c, other switch elements may be used.

Example 4. In the above embodiment, internal signals are used to control the switch elements 7a to 7c, but external signals may also be used, or the switch elements 7a to 7c may be controlled independently for each cell 3a to 3c. The same effect can be achieved even if

Example 5. Further, in the above embodiment, the cell 3d
Although the switching elements 7a to 7c were controlled by focusing on the logic of , the same effect can be achieved by appropriately controlling the switching elements even when focusing on cells having other logics.

[0015]

As described above, according to the present invention, since a switching element is provided between a cell of a master slice LSI and a power supply that drives the cell, unnecessary power consumption can be reduced. There is.

[Brief explanation of the drawing]

FIG. 1: Master slice LS according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of I.

FIG. 2 is a block diagram showing the configuration of a conventional master slice LSI.

[Explanation of symbols]

1a Input port 1b Input port 1c Input port 1d Input port 2 Output port 3a cell 3b cell 3c cell 3d cell 4a Power supply 4b Power supply 4c Power supply 4d Power supply 5 Circuit block 6 Input terminal 7a Switch element 7b Switch element 7c Switch element 8 Pull-down element 9 Control circuit

Claims (1)

[Claims] Claim 1: In a master slice LSI, an MO
A master having a structure in which a switching element is provided between a cell configured using an S transistor and a power source for driving the cell, and the cell can be connected/disconnected from the power source. Slice LSI.