KR100329739B1 - Reference voltage generating circuit having power-down mode for low power consumption - Google Patents

Reference voltage generating circuit having power-down mode for low power consumption Download PDF

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KR100329739B1
KR100329739B1 KR1019950006072A KR19950006072A KR100329739B1 KR 100329739 B1 KR100329739 B1 KR 100329739B1 KR 1019950006072 A KR1019950006072 A KR 1019950006072A KR 19950006072 A KR19950006072 A KR 19950006072A KR 100329739 B1 KR100329739 B1 KR 100329739B1
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current
power
down mode
reference voltage
gate
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KR960035621A (en
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최영식
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

PURPOSE: A reference voltage generation circuit having a power-down mode for a low power consumption is provided to reduce the power consumption by having the power-down mode as offing the reference voltage generation circuit at a point when a reference voltage output is unnecessary. CONSTITUTION: An output node outputs a reference voltage corresponding to a difference between a first current and a second current, A current mirror unit is adjacent to a power voltage supplying source(Vcc) comprised of a plurality of PMOS transistors(MP1 to MP6) for providing the first current to the output node from the power voltage supplying source(Vcc). A current sink unit is connected to a ground voltage supplying unit(Vgnd) comprised of a plurality of NMOS transistors(MN1 to MN6) for providing the second current to the ground voltage supplying unit(Vgnd) from the output node. A power-down mode control unit(200) turns off the NMOS transistors(MN1 to MN6) comprising the current sink in a power-down mode and the PMOS transistors(MP1 to MP6) comprising the current mirror by responding to a control signal(Vi) to block the flow of the first current and the second current..

Description

저전력 소비를 위하여 파워 다운 모드를 가지는 기준전압 발생 회로Voltage Reference Circuit with Power-Down Mode for Low Power Consumption

본 발명은 반도체 소자 동작에 필요한 기준전압(reference voltage)을 생성하는 기준전압 발생 회로에 관한 것으로, 특히 저전력 소비를 필요로 하는 소자에 적용되는 기준전압 발생 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generator circuit for generating a reference voltage required for semiconductor device operation, and more particularly, to a reference voltage generator circuit applied to a device requiring low power consumption.

일반적으로, MOSFET 아날로그 회로 설계시 필수적인 회로 블록 중의 하나가 기준전압 발생회로로서, MOSFET 기준전압 발생회로의 중요성이 부각되고 있다.In general, one of the essential circuit blocks when designing a MOSFET analog circuit is a reference voltage generator circuit, and the importance of the MOSFET reference voltage generator circuit has been highlighted.

제1도는 통상적인 기준전압 발생회로의 일예를 나타내는 회로도로서, 도면에 도시된 바와 같이 전원전압공급원(Vcc) 및 접지전압공급원(Vgnd) 사이의 두 전류경로 상에 전류미러를 구성하는 두 개의 PMOS 트랜지스터 쌍(MP1, MP3), (MP2, MP4)과, 마찬가지로 두 전류경로 상에 전류싱크를 구성하는 두 개의 NMOS 트랜지스터 쌍(MN1, MN3), (MN2, MN4)으로 이루어진다. 그리고 출력단(Vout)이 제4 PMOS 트랜지스터(MP4)와 제3 NMOS 트랜지스터(MN3)를 연결하는 노드(N1)에 형성되어 있다.FIG. 1 is a circuit diagram showing an example of a conventional reference voltage generating circuit, and as shown in the drawing, two PMOSs forming a current mirror on two current paths between a power supply voltage source Vcc and a ground voltage supply source Vgnd. The transistor pairs MP1 and MP3 and MP2 and MP4 are similarly composed of two NMOS transistor pairs MN1 and MN3 and MN2 and MN4 constituting a current sink on two current paths. The output terminal Vout is formed at the node N1 connecting the fourth PMOS transistor MP4 and the third NMOS transistor MN3.

또한, 자체의 전류경로를 통과한 전원전압 공급원의 전류량에 응답하여 동작하도록 제1 PMOS 트랜지스터(MP1), 제2 PMOS 트랜지스터(MP2), 제3 NMOS 트랜지스터(MN3) 및 제4 NMOS 트랜지스터(MN4)의 소오스와 게이트는 공통 접속되어 있다.In addition, the first PMOS transistor MP1, the second PMOS transistor MP2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 to operate in response to the amount of current of the power supply voltage source passing through its current path. The source and the gate of are connected in common.

상기와 같은 종래의 기준전압 발생 회로에서는 출력단(Vout)으로 항상 Vcc와 Vgnd 사이의 소정값을 출력하게 되는 바, 기준전압 출력이 필요치 않은 시점(power down mode)에서도 전류가 계속 흘러 많은 전력을 소비하게 된다는 문제점을 가지고 있다.In the conventional reference voltage generating circuit as described above, a predetermined value between Vcc and Vgnd is always output to the output terminal Vout. Thus, even when the reference voltage output is not required, current flows continuously and consumes a lot of power. I have a problem.

따라서, 본 발명은 기준전압 출력이 필요치 않은 시점에 기준전압 발생회로가 오프(OFF)되어 파워 다운 모드를 가지도록 하므로서 저전력 소자에 접합한 기준 전압 발생 회로를 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a reference voltage generator circuit bonded to a low power device while having a power down mode by turning off the reference voltage generator circuit when a reference voltage output is not required.

상기 목적을 달성하기 위한 본 발명의 기준전압 발생 회로는, 제1전류 및 제2전류 자에 해당하는 기준전압을 출력하는 출력노드; 전원전압공급원(Vcc)에 인접되어 상기 전원전압공급원으로부터 상기 출력노드로 상기 제1전류를 제공하는 다수의 PMOS 트랜지스터로 구성된 전류미러부; 접지전압공급원(Vgnd)에 연결되어 상기 출력노드로부터 상기 접지전압공급원에 상기 제2전류를 제공하는 다수의 NMOS 트랜지스터로 구성된 전류싱크부; 및 제어신호에 응답하여 파워다운모드에서 상기전류 싱크를 구성하는 상기 다수의 NMOS 트랜지스터와 상기 전류미러를 구성하는 상기 다수의 PMOS 트랜지스터를 턴-오프시켜 상기 제1전류 및 제2전류의 흐름을 차단하는 파워다운모드제어수단을 구비하는 것을 특징으로 한다.The reference voltage generation circuit of the present invention for achieving the above object, the output node for outputting a reference voltage corresponding to the first current and the second current ruler; A current mirror unit comprising a plurality of PMOS transistors adjacent to a power supply voltage supply source (Vcc) to provide the first current from the power supply supply source to the output node; A current sink configured to be connected to a ground voltage supply source (Vgnd), the plurality of NMOS transistors providing the second current from the output node to the ground voltage supply source; And turning off the plurality of NMOS transistors constituting the current sink and the plurality of PMOS transistors constituting the current mirror in a power down mode in response to a control signal to block the flow of the first current and the second current. And power down mode control means.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

제2도는 본 발명의 바람직한 실시예에 따른 기준전압 발생 회로도로서, 기준 전압 발생 회로가 사용되지 않는 시점에서 전류미러 및 전류싱크를 구성하고 있는 PMOS 및 NMOS 트랜지스터(MP1 내지 MP4, MN1 내지 MN4)를 모두 오프시켜 기준전압 발생회로를 오프시키도록, 제어신호(Vi)에 응답하여 구동하는 파워다운모드제어부(200)를 포함하여 구성됨을 특징으로 하고 있다.2 is a reference voltage generation circuit diagram according to a preferred embodiment of the present invention, and the PMOS and NMOS transistors MP1 to MP4 and MN1 to MN4 constituting the current mirror and the current sink when the reference voltage generation circuit is not used. And a power down mode control unit 200 which drives in response to the control signal Vi to turn off all of the reference voltage generation circuits.

구체적으로, 본 발명의 기준전압 발생 회로는 제1전류(i1) 및 제2전류(i2) 차(i3= i1- i2)에 해당하는 기준전압(Vout)을 출력하는 출력노드와, 전원전압공급원(Vcc)에 연결되어 상기 전원전압공급원으로부터 상기 출력노드로 상기 제1전류(i1)를 제공하는 다수의 PMOS 트랜지스터(MP1 내지 MP4)로 구성된 전류미러부와, 접지전압공급원(Vgnd)에 연결되어 상기 출력노드로부터 상기 접지전압공급원에 상기 제2전류(i2)를 제공하는 다수의 NMOS 트랜지스터(MN1 내지 MN4)로 구성된 전류싱크부, 및 제어신호(Vi)에 응답하여 파워다운모드에서 상기 전류싱크부를 구성하는 상기 다수의 NMOS 트랜지스터(MN1 내지 MN4)와 상기 전류미러부를 구성하는상기 다수의 PMOS 트랜지스터(MP1 내지 MP4)를 턴-오프시켜 상기 제1전류(i1) 및 제2전류(i2)의 흐름을 차단하는 파워다운모드제어부(200)로 구성된다.Specifically, the reference voltage generator circuit of the present invention outputs a reference voltage Vout corresponding to the difference between the first current i 1 and the second current i 2 (i 3 = i 1 -i 2 ). And a current mirror unit comprising a plurality of PMOS transistors MP1 to MP4 connected to a power supply voltage supply source Vcc to provide the first current i 1 from the power supply supply source to the output node, and a ground voltage supply source. A current sink comprising a plurality of NMOS transistors MN1 to MN4 connected to Vgnd to provide the second current i 2 from the output node to the ground voltage supply source, and in response to a control signal Vi. In the power-down mode, the plurality of NMOS transistors MN1 to MN4 constituting the current sink unit and the plurality of PMOS transistors MP1 to MP4 constituting the current mirror unit are turned off to thereby turn on the first current i 1 . And a power down mode agent that blocks the flow of the second current i 2 . It consists of a fisherman 200.

파워다운모드제어부(200)는 기준전압 출력(Vout)이 필요치 않는 시점(즉, 파워다운모드)에서 논리레벨 '하이'에 해당하는 제어신호(Vi)를 입력받아 접지전압(Vgnd)을 전류싱크를 구성하는 다수의 NMOS 트랜지스터(MN1 내지 MN4)의 게이트에 전달하는 패스게이트(MN5, MP5), (MN6, MP6)로 실시 구성되어 있다. 즉, 상기 제어신호(Vi)를 게이트로 입력받는 제5 NMOS 트랜지스터(MN5) 및 제1인버터(INV1)를 통해 상기 제어신호(Vi)의 반전신호를 게이트로 입력받는 제5 PMOS 트랜지스터(MP5) 쌍으로 이루어진 제1패스게이트와, 상기 제어신호(Vi)를 게이트로 입력받는 제6 NMOS 트랜지스터(MN6) 및 제2인버터(INV2)를 통해 상기 제어신호(Vi)의 반전신호를 게이트로 입력받는 제6 PMOS 트랜지스터(MP6) 쌍으로 이루어진 제2패스게이트로 파워다운모드제어부가 구성되어, 제1 및 제2 패스게이트가 제어신호(Vi)에 의해 턴온될 시(즉, 파워다운모드임을 알리는 제어신호 Vi이 활성화될 때) 전류싱크를 구성하는 NMOS 트랜지스터(MN1 내지 MN4)의 게이트에는 접지전압(Vgnd)이 인가된다.The power-down mode controller 200 receives a control signal Vi corresponding to a logic level 'high' at a time when the reference voltage output Vout is not required (that is, power-down mode) and current-sinks the ground voltage Vgnd. The pass gates MN5 and MP5 and MN6 and MP6 which are transferred to the gates of the plurality of NMOS transistors MN1 to MN4 constituting the circuit are implemented. That is, the fifth PMOS transistor MP5 receiving the inverted signal of the control signal Vi through the fifth NMOS transistor MN5 and the first inverter INV1 receiving the control signal Vi as the gate. Receiving an inverted signal of the control signal Vi through the sixth NMOS transistor MN6 and the second inverter INV2 receiving the pair of the first pass gate and the control signal Vi as the gate. The power down mode control unit includes a second pass gate formed of a sixth PMOS transistor MP6 pair, and controls the first and second pass gates when the first and second pass gates are turned on by the control signal Vi (that is, the power down mode). When the signal Vi is activated), the ground voltage Vgnd is applied to the gates of the NMOS transistors MN1 to MN4 constituting the current sink.

결국, NMOS 트랜지스터(MN1 내지 MN4)의 게이트에 접지전원(Vgnd)이 인가되면, 즉, 파워다운모드제어부(200)에 입력되는 제어신호(Vi)에 논리레벨 '하이' 값이 입력되면 제5 NMOS 트랜지스터(MN5)와 제6 NMOS 트랜지스터(MN6)가 온(ON)되고, 제5 PMOS 트랜지스터(MP5)와 제6 PMOS 트랜지스터(MP6) 역시 온되어접지전압(Vgnd)이 전류싱크를 구성하는 NMOS 트랜지스터(MN1 내지 MN4)의 게이트에 인가되면, NMOS 트랜지스터(MN1 내지 MN4)들은 오프(OFF)되며, 전류미러를 구성하는 PMOS 트랜지스터(MP1 내지 MP4)의 게이트 전압은 공급전원(Vcc) 레벨로 증가하여 역시 오프 된다.As a result, when the ground power source Vgnd is applied to the gates of the NMOS transistors MN1 to MN4, that is, when the logic level 'high' value is input to the control signal Vi input to the power-down mode controller 200, the fifth voltage is applied. The NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on, and the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are also turned on so that the ground voltage Vgnd constitutes a current sink. When applied to the gates of the transistors MN1 to MN4, the NMOS transistors MN1 to MN4 are turned off, and the gate voltages of the PMOS transistors MP1 to MP4 constituting the current mirror are increased to the power supply voltage Vcc level. Is also off.

따라서, 기준전압발생회로는 오프되어 전원전압공급원(Vcc)과 접지전압공급원(Vgnd) 사이의 전류 흐름이 차단되므로써 전력이 소비되지 않는다.Therefore, the reference voltage generating circuit is turned off so that the current flow between the power supply voltage supply source Vcc and the ground voltage supply source Vgnd is cut off, so that no power is consumed.

이상, 상기 설명과 같이 이루어지는 본 발명은 기준전압 출력이 필요치 않은 시점에서 파워다운모드를 가지는 기준전압 발생 회로를 제공하므로써 전력 소비를 극소화하는 효과가 있다.As described above, the present invention as described above has the effect of minimizing power consumption by providing a reference voltage generating circuit having a power-down mode when the reference voltage output is not required.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

제1도는 종래의 기준전압 발생 회로도,1 is a conventional reference voltage generation circuit diagram,

제2도는 본 발명의 바람직한 실시예에 따른 기준전압 발생 회로도.2 is a reference voltage generation circuit diagram according to a preferred embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

200 : 스위칭 회로200: switching circuit

MP1 내지 MP6 : PMOS 트랜지스터MP1 to MP6: PMOS transistor

MN1 내지 MN6 : NMOS 트랜지스터MN1 to MN6: NMOS transistor

Claims (4)

기준전압 발생 회로에 있어서,In the reference voltage generating circuit, 제1전류 및 제2전류 차에 해당하는 기준전압을 출력하는 출력노드;An output node for outputting a reference voltage corresponding to the difference between the first current and the second current; 전원전압공급원(Vcc)에 인접되어 상기 전원전압공급원으로부터 상기 출력노드로 상기 제1전류를 제공하는 다수의 피모스트랜지스터로 구성된 전류미러부;A current mirror unit configured to be adjacent to a power supply voltage supply source (Vcc) and configured to provide the first current from the power supply supply source to the output node; 접지전압공급원(Vgnd)에 연결되어 상기 출력노드로부터 상기 접지전압공급원에 상기 제2전류를 제공하는 다수의 엔모스트랜지스터로 구성된 전류싱크부; 및A current sink configured to be connected to a ground voltage supply source (Vgnd), the plurality of enMOS transistors providing the second current from the output node to the ground voltage supply source; And 제어신호(Vi)에 응답하여 파워다운모드에서 상기 전류 싱크를 구성하는 상기 다수의 엔모스트랜지스터와 상기 전류미러를 구성하는 상기 다수의 피모스트랜지스터를 턴-오프시켜 상기 제1전류 및 제2전류의 흐름을 차단하는 파워다운모드제어수단을 구비하는 것을 특징으로 하는 기준전압 발생 회로.Turn the plurality of PMOS transistors constituting the current mirror and a plurality of NMOS transistor and the forming the current sink from the control signal (V i) in response to the power down mode-off by the first current and the second And a power down mode control means for interrupting the flow of current. 제1항에 있어서,The method of claim 1, 상기 전류미러부는 상기 전원전압공급원(Vcc) 및 상기 접지전압공급원(Vgnd) 사이의 두 전류경로 상에 전류미러를 구성하는 제1 및 제2 피모스트랜지스터쌍으로 이루어지고,The current mirror part includes a first and a second PMOS transistor pair constituting a current mirror on two current paths between the power supply voltage source Vcc and the ground voltage supply source Vgnd, 상기 전류싱크부는 상기 전원전압공급원(Vcc) 및 상기 접지전압공급원(Vgnd) 사이의 두 전류경로 상에 전류싱크를 구성하는 제1 및 제2 엔모스트랜지스터쌍으로이루어짐을 특징으로 하는 기준전압 발생 회로.The current sink unit is formed of a reference voltage generating circuit comprising first and second enMOS transistor pairs constituting a current sink on two current paths between the power supply voltage source Vcc and the ground voltage supply source Vgnd. . 제1항에 있어서,The method of claim 1, 상기 파워다운모드제어수단은,The power down mode control means, 파워다운모드에서 논리레벨 '하이'에 해당하는 상기 제어신호를 입력받아 상기 전류싱크를 구성하는 다수의 엔모스트랜지스터의 게이트에 접지전압(Vgnd)을 전달하는 패스게이트를 포함하는 것을 특징으로 하는 기준전압 발생 회로.And a pass gate configured to receive the control signal corresponding to a logic level 'high' in a power-down mode and transfer a ground voltage Vgnd to gates of a plurality of NMOS transistors constituting the current sink. Voltage generating circuit. 제2항에 있어서,The method of claim 2, 상기 파워다운모드제어수단은,The power down mode control means, 상기 제어신호를 게이트를 입력받는 제1엔모스트랜지스터 및 제1인버터를 통해 상기 제어신호의 반전신호를 게이트로 입력받는 제1피모스트랜지스터로 이루어져 접지전압을 상기 제1엔모스트랜지스터쌍의 각 게이트로 전달하는 제1패스게이트; 및A gate of the first NMOS transistor pair includes a first NMOS transistor that receives the control signal as a gate and a first PMOS transistor that receives the inverted signal of the control signal as a gate through a first inverter. A first passgate transferred to the first passgate; And 상기 제어신호를 게이트로 입력받는 제2엔트랜지스터 및 제2인버터를 통해 상기 제어신호의 반전신호를 게이트로 입력받는 제2피모스트랜지스터로 이루어져 접지전압을 상기 제2엔모스트랜지스터쌍의 각 게이트로 전달하는 제2패스게이트로 구성됨을 특징으로 하는 기준전압 발생 회로.A second MOS transistor receiving the control signal as a gate and a second PMOS transistor receiving the inverted signal of the control signal as a gate through a second inverter and a ground voltage to each gate of the second NMOS transistor pair. And a second pass gate configured to transmit the reference voltage.
KR1019950006072A 1995-03-22 1995-03-22 Reference voltage generating circuit having power-down mode for low power consumption KR100329739B1 (en)

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