KR20030046223A - Semiconductor memory device with multiple internal supply voltage - Google Patents

Abstract

PURPOSE: A semiconductor memory device with plural internal supply voltage sources is provided to select necessary voltages by using a voltage selection circuit and a plurality of voltage pads. CONSTITUTION: A semiconductor memory device comprises a package power pin(10), a power pad(21), a voltage selection circuit(22), an internal reference voltage generation circuit(24), and a DC voltage generation circuit(25). The power pad receives the supply voltage from the package power pin and supplies the supply voltage to each circuit block. The voltage selection circuit receives the first reference voltage and an MRS control signal and outputs selection signals. The internal reference voltage generation circuit receives the selection signals and generates the internal reference voltage. The DC voltage generation circuit receives signals from the internal reference voltage generation circuit and generates the internal DC voltage.

Description

A semiconductor memory device having a plurality of internal power supply voltages {SEMICONDUCTOR MEMORY DEVICE WITH MULTIPLE INTERNAL SUPPLY VOLTAGE}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of internal power supply voltages.

Recently, with the reduction of power, semiconductor memory devices are required to design options for general chips and low power chips.

Conventionally, in the case of a semiconductor memory device requiring a plurality of power supply voltages, a metal option is used to select a required voltage. However, to select a power supply voltage using the metal option, a different mask must be manufactured for each required voltage and a different metal process must be performed. In addition, selecting the supply voltage using the metal option requires a different test program for each required voltage and a different delay control circuit.

It is an object of the present invention to provide a semiconductor memory device having a plurality of internal power supply voltages capable of selecting a required voltage without using a metal option.

1 is a view illustrating an embodiment of a semiconductor memory device having a plurality of internal power supply voltages according to the present invention.

2 is an embodiment of an internal reference voltage generation circuit of the semiconductor device according to the present invention.

3 is a diagram illustrating another embodiment of a semiconductor memory device having a plurality of internal power supply voltages according to the present invention.

4 is a diagram illustrating an example in which a selection signal generated according to the present invention is applied to an output driver circuit.

5 is a diagram illustrating an example in which a selection signal generated according to the present invention is applied to an internal power supply voltage generation circuit for an array.

<Description of the symbols for the main parts of the drawings>

10: package power pin 20: semiconductor chip

21: power pad 22: voltage selection circuit

23: first to nth voltage pads 24: internal reference voltage generating circuits

25 DC voltage generating circuits 26 MRS control circuit

31, 41: differential amplifier 32: output buffer

42: pulse generator circuit

According to an exemplary embodiment of the present invention, a semiconductor memory device having a plurality of internal power supply voltages may include a voltage selection circuit configured to receive a pad control signal from a power pad and output a plurality of selection signals; And a plurality of voltage pads for receiving a corresponding selection signal among the plurality of selection signals from the voltage selection circuit.

In addition, a semiconductor memory device having a plurality of internal power supply voltages according to the present invention includes: a voltage selection circuit that receives an MRS control signal from a mode register set (MRS) control circuit and outputs a plurality of selection signals; And a plurality of internal reference voltage generation circuits configured to receive a corresponding selection signal among the plurality of selection signals from the voltage selection circuit and generate an internal reference voltage.

Hereinafter, a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

1 is a view illustrating an embodiment of a semiconductor memory device having a plurality of internal power supply voltages according to the present invention.

1 is a semiconductor memory device having a plurality of internal power supply voltages for selecting a required voltage using a bonding pad control signal, and receives a power supply voltage VDD or VSS from a package power supply pin 10 and a package power supply pin 10. And receiving a pad control signal from a first reference voltage and a power pad 21 for supplying a power supply voltage (VDD or VSS) to circuit blocks in the semiconductor chip 20, and selecting first to nth. A voltage selection circuit 22 for outputting a signal, first to nth voltage pads 23 for receiving a corresponding selection signal among the first to nth selection signals from the voltage selection circuit 22, and first to nth Internal reference voltage generation circuits 24 for receiving a signal from each of the voltage pads 23 and generating an internal reference voltage, DC for receiving a signal from each of the internal reference voltage generation circuits 24 and generating an internal DC voltage. To obtain the voltage generating circuits 25 And.

Hereinafter, the operation of the semiconductor memory device of FIG. 1 will be described.

The power pad 21 receives the power supply voltage VDD or VSS from the package power supply pin 10 and supplies the power supply voltage VDD or VSS to circuit blocks in the semiconductor chip 20. When a power supply voltage is supplied to the semiconductor chip 20, the first reference voltage generated is the first reference voltage. When the first reference voltage is set after power is supplied to the system, the voltage selection circuit 22 receives the pad control signal from the first reference voltage and the power pad 21 and generates a selection signal for selecting the required voltage. . The selected ones of the first to nth selection signals are applied to the corresponding internal reference voltage generation circuits of the internal reference voltage generation circuits 24 through corresponding voltage pads of the first to nth voltage pads 23. Each of the selected internal reference voltage generators generates a reference voltage and is applied to the corresponding DC voltage generator 25. Each DC voltage generator generates different DC voltage levels.

2 is a detailed diagram of an internal reference voltage generation circuit of a semiconductor device according to an embodiment of the present invention, in which a differential amplifier 31 is applied with a first reference voltage from a first input terminal and outputs a second reference voltage, and a power supply voltage VDD. ) And the drains of the P-type metal oxide semiconductor (PMOS) transistors MP1 and MP2 and PMOS transistors MP2 connected in series between the output terminals of the differential amplifier 31 and the gate and drain terminals are shorted, respectively. A PMOS transistor MP3 connected between the terminal and the source terminal and having a gate terminal for receiving a selection signal, and a second input terminal of the source terminal and the differential amplifier 31 connected to the output terminal of the differential amplifier 31. A PMOS transistor MP4 having a gate terminal connected to and having a drain terminal and a gate terminal shorted to each other, and a drain terminal of the PMOS transistor MP4. Has a drain terminal coupled to the source terminal and the ground with a gate terminal and a drain terminal and a PMOS transistor (MP5) is short-circuited to each other.

Hereinafter, the operation of the internal reference voltage generator circuit of FIG. 2 will be described.

One of the selection signals generated in the voltage selection circuit 22 of FIG. 1 is applied to the gate terminal of the PMOS transistor MP3. When the selection signal applied is low, the PMOS transistor MP3 is turned on so that the second reference voltage is lowered by the PMOS transistor MP1 by 1VTP, which is the threshold voltage of the PMOS transistor MP1 from the power supply voltage VDD. When the selection signal to be applied is high, the PMOS transistor MP3 is turned off so that the second reference voltage is lowered by 2VTP from the power supply voltage VDD by the PMOS transistor MP1 and the PMOS transistor MP2. The differential amplifier 31 stabilizes the second reference voltage by amplifying a difference between the first reference voltage applied to the first input terminal and the voltage fed back from the drain terminal of the PMOS transistor MP4.

3 is a view illustrating another embodiment of a semiconductor memory device having a plurality of internal power supply voltages according to the present invention, in which a signal controlling the voltage selection circuit 22 to select a required voltage is not a pad control signal, but an MRS control. Same as the embodiment of FIG. 1 except that it is a signal and there are no voltage pads 23.

In the semiconductor memory device having a plurality of internal power supply voltages according to the present invention shown in FIG. A power pad 21 for supplying a power supply voltage VDD or VSS to the circuit blocks, a voltage selection for receiving an MRS control signal from the first reference voltage and the MRS control circuit 26 and outputting first to nth selection signals Internal reference voltage generation circuits 24 and internal reference voltage generation circuits for receiving the selected selection signal of the first to nth selection signals from the circuit 22, the voltage selection circuit 22 and generating an internal reference voltage ( 24) DC voltage generation circuits 25 for receiving a signal from each and generating an internal DC voltage.

Hereinafter, the operation of the semiconductor memory device of FIG. 3 will be described.

The power pad 21 receives the power supply voltage VDD or VSS from the package power supply pin 10 and supplies the power supply voltage VDD or VSS to circuit blocks in the semiconductor chip 20. When a power supply voltage is supplied to the semiconductor chip 20, the first reference voltage generated is the first reference voltage. When the first reference voltage is set after the system is powered on, the voltage selection circuit 22 receives the MRS control signal from the first reference voltage and the MRS control circuit 26 and generates a selection signal for selecting the required voltage. Let's do it. The selected ones of the first to nth selection signals are applied to the corresponding internal reference voltage generation circuit among the internal reference voltage generation circuits 24. Each of the selected internal reference voltage generators generates a reference voltage and is applied to the corresponding DC voltage generator 25. Each DC voltage generator generates different DC voltage levels.

4 is a diagram illustrating an example in which a selection signal generated according to the present invention is applied to an output driving circuit, and is connected to an output buffer 32, a drain terminal connected to an output driving power supply voltage VDDQ, and a node N2. N-type MOS transistor MN1 having a source terminal and a gate terminal to which an output of the output buffer 32 is applied, a drain terminal connected to an output driving power supply voltage VDDQ, and a first selection signal. Is connected to the NMOS transistor MN4 having the gate terminal to which the gate is applied, the drain terminal connected to the source terminal of the NMOS transistor MN4, the source terminal connected to the node N2, and the gate terminal of the NMOS transistor MN1. An NMOS transistor MN2 having a gate terminal having a gate terminal therein, an NMOS transistor MN5 having a drain terminal connected to an output driving power supply voltage VDDQ, and a gate terminal to which a second selection signal is applied, and an NMOS transistor MN5 NMOS transistor (MN3) having a drain terminal connected to the source terminal of the ()), a source terminal connected to the node (N2) and a gate terminal connected to the gate terminal of the NMOS transistor (MN2).

Hereinafter, the operation of the output driver circuit shown in FIG. 4 will be described.

When the output of the output buffer 32 is high and both of the NMOS transistors MN1 to MN3 are turned on, when the first selection signal and the second selection signal are both low, the NMOS transistors MN4 and MN5 are turned off. Only the NMOS transistor MN1 contributes to the output current. When the output of the output buffer 32 is high and both of the NMOS transistors MN1 to MN3 are turned on, when the first select signal and the second select signal are both high, the NMOS transistors MN4 and MN5 are turned on. NMOS transistors MN1 to MN3 all contribute to the output current.

Therefore, the magnitude of the output current of the output driver circuit can be adjusted by the selection signal generated by the present invention.

5 is a diagram illustrating an example in which a selection signal generated according to the present invention is applied to an internal power supply voltage generation circuit for an array, wherein an array reference voltage is applied to a first input terminal and fed back to the second input terminal. It has a gate which has a voltage applied and a differential amplifier 41 generating an input voltage of an internal power supply driving circuit for the array, a source terminal to which the array power supply voltage VDDA is applied, and a drain terminal connected to the output terminal of the differential amplifier 41. A PMOS transistor (MP6) having a terminal and a drain terminal shorted to each other, an NMOS transistor (MN6) having a drain terminal connected to the output terminal of the differential amplifier 41 and a source terminal connected to ground, and a selection signal being received and pulsed A pulse generating circuit 42 for generating a signal and transmitting it to the gate terminal of the NMOS transistor MN6 is provided.

Hereinafter, the operation of the internal power supply voltage generator circuit for the array of FIG. 5 will be described.

A pulse is generated by the selection signal applied to the pulse generator circuit 42. In the high state of this pulse, the NMOS transistor MN6 is turned on so that the level of the node N3 becomes low. At this time, the input voltage of the internal power supply driving circuit for the array becomes low.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, a semiconductor memory device having a plurality of internal power supply voltages according to the present invention can select a required voltage without using a metal option.

Claims (5)

A voltage selection circuit that receives a pad control signal from a power pad and outputs a plurality of selection signals; And a plurality of voltage pads for receiving a corresponding selection signal among the plurality of selection signals from the voltage selection circuit. The method of claim 1, And a plurality of internal reference voltage generation circuits for receiving signals from the plurality of voltage pads to generate internal reference voltages, respectively. The method of claim 1, And a plurality of DC voltage generation circuits for receiving signals from the plurality of internal reference voltage generation circuits to generate different DC voltages, respectively. A voltage selection circuit receiving the MRS control signal from the MRS control circuit and outputting a plurality of selection signals; And a plurality of internal reference voltage generating circuits configured to receive a corresponding selection signal among the plurality of selection signals from the voltage selection circuit and generate an internal reference voltage. The method of claim 4, wherein And a plurality of DC voltage generation circuits for receiving signals from the plurality of internal reference voltage generation circuits to generate different DC voltages, respectively.