KR100239593B1 - Current supply circuit which can control level - Google Patents

Abstract

The present invention relates to a level-adjustable current supply circuit that can operate with more than one current supply source. The level-adjustable current supply circuit includes a first transistor having one end connected to a voltage supply terminal and receiving an input signal in common. A second transistor, a current output terminal connected to the other end of the second transistor, a third transistor connected at one end to the other end of the first transistor and connected at the other end to the ground terminal, and operated under an arbitrary bias; And a level adjusting unit connected between one end of the second transistor and one end of the third transistor to receive a selection signal and serve as a switching element.

Description

Level supply current supply circuit

The present invention relates to a current supply circuit and, more particularly, to a level adjustable current supply circuit that can operate with one or more current sources.

Hereinafter, a conventional current supply circuit will be described with reference to the accompanying drawings.

1 is a circuit diagram showing a conventional current supply circuit.

In the conventional current supply circuit, as shown in FIG. 1, the first PMOS transistor PM1 and the second PMOS transistor PM2 generating current according to the supply voltage and the bias signal An NMOS transistor NM mirroring current generated through the first and second PMOS transistors.

Gates of the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected to each other, and the gate and the source terminal of the first PMOS transistor PM1 are connected to each other.

The drain terminal of the NMOS transistor NM is connected to the source terminal of the first PMOS transistor PM1.

Referring to the operation of the conventional current supply circuit configured as described above are as follows.

First, when the NMOS transistor is turned on by applying a bias voltage to the NMOS transistor NM, the third current I ₃ flows through the NMOS transistor. Since the input impedance of the first PMOS transistor PM1 and the second PMOS transistor PM2 is infinity (∞), the first current I ₁ flowing through the first PMOS transistor PM1 is negative. It becomes equal to the third current I ₃ flowing through the MOS transistor.

In addition, since the voltages of the gate and the source of the first PMOS transistor PM1 and the second PMOS transistor PM2 are the same, the output current may be reduced by the size ratio K between the first PMOS transistor and the NMOS transistors. Io) becomes Io = K × I ₁ = K × I ₂ .

This current supply circuit is used only as a current supply source.

The conventional current supply circuit as described above has the following problems.

Since one current supply circuit can obtain one current source with one current supply circuit, when another current supply source is required, an additional current supply circuit must be configured, so the integration of the device is reduced.

An object of the present invention is to provide a current supply circuit that can provide one or more current sources to solve the above problems.

1 is a circuit diagram showing a conventional current supply circuit

Figure 2 is a circuit diagram showing a current supply circuit capable of adjusting the level of the present invention

Figure 3 is a circuit diagram showing the first drive of the current supply circuit capable of adjusting the level of the present invention

Figure 4 is a circuit diagram showing the second drive of the current supply circuit capable of adjusting the level of the present invention

Explanation of symbols for the main parts of the drawings

PM1, PM2, PM3: first, second and third PMOS transistors

NM1, NM2: first and second NMOS transistors

Vdd: Supply Voltage Vss: Ground Voltage

In order to achieve the above object, the level-adjustable current supply circuit of the present invention has one end connected to a voltage supply terminal and connected to a first transistor, a second transistor, and the other end of the second transistor in common. Between a current output terminal, a third transistor having one end connected to the other end of the first transistor and the other end connected to the ground terminal, and operated under an arbitrary bias; and between one end of the first and second transistors and one end of the third transistor. It is characterized in that it is configured to include a level adjustment unit connected to the receiving element to serve as a switching element.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram showing a current supply circuit capable of adjusting the level of the present invention, FIG. 3 is a circuit diagram showing a first drive of the current supply circuit capable of adjusting the level of the present invention, and FIG. 4 is a level diagram of the present invention. This is a circuit configuration diagram shown in accordance with the second driving of the possible current supply circuit.

First, as shown in FIG. 2, the configuration of the current supply circuit capable of adjusting the level includes a selection signal S for selecting a current source, and a third PMOS transistor PM3 operating by receiving the selection signal S. FIG. ) And a second NMOS transistor NM2, and a first PMOS transistor PM1 and a second P for generating a current source according to the third PMOS transistor PM3 and the second NMOS transistor NM2. It is comprised including the MOS transistor PM2 and the 1st NMOS transistor NM1.

In this case, the gates of the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected, and one end of each of the first and second PMOS transistors is connected to the supply voltage Vdd terminal.

One end of the first NMOS transistor NM1 is connected to the other end of the first PMOS transistor PM1, and a current I ₀ is generated at the other end of the second PMOS transistor PM2.

The third PMOS transistor PM3 and the second NMOS transistor NM2 form a CMOS transistor. A supply voltage terminal is connected to one end of the third PMOS transistor PM3, and the other end of the third PMOS transistor PM3. A gate end of the first PMOS transistor PM1 and one end of the second NMOS transistor NM2 are connected, and another end of the second NMOS transistor NM2 is connected to one end of the first NMOS transistor NM1. It is. The third PMOS transistor PM3 and the second NMOS transistor NM2 are driven by receiving the selection signal S. FIG. Here, the third PMOS transistor PM3 and the second NMOS transistor NM2 receive a selection signal S to act as a switching role to adjust the level.

Hereinafter, the operation of the current drive circuit capable of adjusting the level of the present invention will be described.

First, when the signal of the selection signal S is 'high', the third PMOS transistor PM3 is turned off, and the second NMOS transistor NM2 is turned on to operate as in the prior art.

On the contrary, when the selection signal S is 'low', the second NMOS transistor NM2 is turned off and the third PMOS transistor PM3 is turned on so that the first PMOS transistor is shown in FIG. 4. And one end and the gate terminal of the second PMOS transistor are connected to the supply voltage terminal. Therefore, the output current Io can be adjusted by the self bias of the second PMOS transistor PM2.

The current supply circuit capable of adjusting the level of the present invention as described above has the following effects.

If another current source to be supplied to the circuit is needed, an existing circuit can be used as it is because the current is generated by the bias of the second PMOS transistor by changing the selection signal without adding a circuit to supply a new current source. This is effective for integrating the device.

Claims (5)

A first transistor and a second transistor, each end of which is connected to a voltage supply terminal and which receives an input signal in common; A current output terminal connected to the other end of the second transistor, A third transistor having one end connected to the other end of the first transistor and the other end connected to the ground terminal and operated under an arbitrary bias; And a level adjustment unit connected between one end of the first and second transistors and one end of the third transistor to receive a selection signal to serve as a switching element. 2. The current supply circuit of claim 1, wherein the level adjustment unit comprises a CMOS transistor. 2. The current supply circuit of claim 1, wherein the first and second transistors are PMOS transistors. The current supply circuit of claim 1, wherein the third transistor is configured of an NMOS transistor. 3. The PMOS transistor according to claim 2, wherein a PMOS transistor is present between one end of the first and second transistors among the CMOS transistors and the gates of the first and second transistors, and the gates of the first and second transistors and the first transistor. A current supply circuit with a level adjustment, characterized in that it is composed of NMOS transistors between the other ends.

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