JPS622656A - Semiconductor protecting device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor protecting device, whose voltage protecting range is broad, by connecting one of two diffused layer regions, whose conducting type is different from that of a semiconductor substrate or an island region, to a potential, which is different from a potential, to which the semiconductor substrate, the island region or the source of a field effect transistor is connected. CONSTITUTION:On the surface of a P-type semiconductor substrate 1, N-type diffused layer regions 2 are provided at two places. Thus an NPN bipolar transistor is formed. One N-type diffused layer region 2 is connected to an external connecting terminal 101. The P-type semiconductor substrate 1 is connected to the ground potential. The other N-type diffused layer region 2 is connected to a power source voltage terminal 102, whose potential is different from the source potential of an N-type field effect transistor. Thus the keeping voltage can be made high without adding any process to the manufacturing processes. Therefore, the voltage protecting range can be widened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor protection device, and more particularly to a semiconductor protection device for an integrated circuit using a bipolar transistor as a protection element.

[Conventional technology]

Conventionally, a semiconductor protection device using a bipolar transistor as a protection element has been developed using a bipolar transistor, for example, a
It was constructed by installing two N-type diffusion layer regions 2 on the surface of a type semiconductor substrate 1, connecting them to a -perfect external connection terminal 101, and connecting the other to the ground potential. The equivalent circuit is shown in FIG. 5, and the voltage/current characteristics seen from the external connection terminal 101 are shown in FIG. 6 in the case of a bipolar transistor that can be formed on a semiconductor integrated circuit with a power supply voltage Vcc of about 5V.

The holding voltage of the conventional example shown in FIG. 4 is the power supply voltage ■ as shown in FIG. . It is higher, about 8■. For example, if this device is used as a protection element for a terminal to which a voltage higher than the holding voltage and lower than the breakdown voltage is supplied, the terminal may become higher than the breakdown voltage of 16V due to noise etc. and enter the negative resistance region. If this occurs, the voltage supplied to this terminal is higher than the holding voltage, so a state in which a large current continues to flow will be maintained, eventually causing the aluminum wiring to melt or the bond to deteriorate.

[Problem that the invention seeks to solve]

The above-described conventional semiconductor protection device has a drawback that the protection voltage range is narrow because the holding voltage is not very high relative to the power supply voltage.

An object of the present invention is to provide a semiconductor protection device with a wide protection voltage range.

[Means for solving problems]

The semiconductor protection device of the present invention includes a semiconductor substrate or island-like region of a first conductivity type and two diffusion layer regions of a second conductivity type formed close to each other on the surface thereof. One of the diffusion regions is connected directly or through a resistor to an external connection terminal, and the other is different from a potential at which the semiconductor substrate, the island region, or the source of the insulated gate field effect transistor of the second conductivity type is connected. It is configured by connecting to a potential.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional horizontal view showing one embodiment of the present invention.

In the embodiment shown in FIG. 1, an NPN bipolar transistor is formed by providing two N-type diffusion layer regions 2 on the surface of a P-type semiconductor substrate 1.
It is connected to the external connection terminal i01, and the P-type semiconductor substrate 1 is connected to the ground potential 1c, which is different from the source potential (usually the ground potential) of the other N-type diffusion layer region 2t-N-type field effect transistor (not shown). It is configured to be connected to the power supply voltage terminal 102.

Figure 2 shows its equivalent circuit, and Figure 3 shows its voltage/voltage.
Shows j-ness. In Fig. M3, the broken line a is the characteristic of the embodiment shown in Fig. 1, and the broken line s is the characteristic of the conventional example shown in Fig. 4.
(same as the broken line in FIG. 6).

As shown in FIG. 3, the holding voltage is approximately the power supply voltage Vcc.
(5V), and in the conventional example shown in Fig. 4, it is 8V.
However, in the embodiment shown in FIG. 1, it becomes 13V. In addition, the voltage and current entering the negative resistance region also increase. As explained above, in the embodiment shown in FIG. The holding voltage can be increased by increasing the power supply voltage■. This NPN transistor is used as protection for a terminal to which a voltage higher than C and lower than the holding voltage is supplied, so that even if the potential of this terminal exceeds the breakdown voltage and enters the negative resistance region due to noise etc., the terminal will remain in the negative resistance region. Once the voltage returns to normal, it is lower than the holding voltage, so a large current will not continue to flow, and the protection element will not be destroyed due to melting of the aluminum wiring or deterioration of the bond.

In the embodiment shown in FIG. 1, the potential of one side of the N-type diffusion region 2 is set to the power supply voltage ■cc, but this potential is equal to the potential of the P-type semiconductor substrate 1 (or the source of the N-type field effect transistor). The higher the potential is, the higher the holding voltage will be.

Furthermore, the same effect can be obtained by providing a resistor between the external connection terminal 101 and one of the N-type diffusion layer regions 2 connected thereto in the embodiment shown in FIG.

Although the present invention has been described above in detail with respect to the case where a P-type substrate is used, the same applies to the case where an N-type diffusion layer is formed in the P-well region.

〔Effect of the invention〕

As explained in detail above, the semiconductor protection device of the present invention includes:
One of the two diffusion layer regions of a conductivity type different from that of the semiconductor substrate or island region is connected to the potential at which the source of the semiconductor substrate/island region or the 'It field effect transistor (of the same conductivity type as this diffusion layer region) is connected. By connecting to a potential different from
This has the effect that the holding voltage can be increased without adding any process to the manufacturing process, and therefore the protection voltage range can be widened.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional model diagram showing one embodiment of the semiconductor protection device of the present invention, Figs. 2 and 3 are a circuit diagram and a graph showing voltage/current characteristics of the embodiment shown in Fig. 1, and Fig. 4 5 is a cross-sectional model diagram showing an example of a conventional semiconductor protection device, and FIGS. 5 and 6 are a circuit diagram and a graph showing voltage/current characteristics of the conventional example shown in FIG. 4. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type diffusion layer region, 101... External grounding terminal, 102...
...Power supply voltage terminal. Kaya 1 Rice field broom 2 Kouka 5 Diagram

Claims (1)

[Claims] In a semiconductor protection device comprising a semiconductor substrate or island-like region of a first conductivity type and two diffusion layer regions of a second conductivity type formed close to each other on the surface thereof, one of the diffusion layer regions is directly or It is characterized in that it is connected to an external connection terminal via a resistor, and the other end is connected to a potential different from the potential to which the semiconductor substrate, the island-like region, or the source of the insulated gate field effect transistor of the second conductivity type is connected. Semiconductor protection equipment.