JPH0528493B2 - - Google Patents
Info
- Publication number
- JPH0528493B2 JPH0528493B2 JP60141714A JP14171485A JPH0528493B2 JP H0528493 B2 JPH0528493 B2 JP H0528493B2 JP 60141714 A JP60141714 A JP 60141714A JP 14171485 A JP14171485 A JP 14171485A JP H0528493 B2 JPH0528493 B2 JP H0528493B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- potential
- diffusion layer
- semiconductor
- protection device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体保護装置に関し、特にバイポー
ラトランジスタを保護素子とする、集積回路の半
導体保護装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor protection device, and particularly to a semiconductor protection device for an integrated circuit using a bipolar transistor as a protection element.
従来、バイポーラトランジスタを保護素子とす
る半導体保護装置は、第4図の断面模型図に示す
様に、例えばP型半導体基板1の表面にN型拡散
層領域2を2箇所設置し、一方を外部接続端子1
01に接続し、他方を接地電位に接続する事によ
つて構成されていた。その等価回路を第5図、又
電源電圧Vccが5V程度の半導体集積回路上に形成
可能なバイポーラトランジスタとした場合の外部
接続端子101から見た電圧・電流特性を第6図
に示す。
Conventionally, a semiconductor protection device using a bipolar transistor as a protection element has, as shown in the cross-sectional model diagram in FIG. Connection terminal 1
01 and the other to ground potential. The equivalent circuit is shown in FIG. 5, and the voltage/current characteristics seen from the external connection terminal 101 in the case of a bipolar transistor that can be formed on a semiconductor integrated circuit with a power supply voltage Vcc of about 5V are shown in FIG.
第4図に示す従来例の保持電圧は、第6図に図
示するように電源電圧Vccより高く、8V程度とな
る。ここで例えば、この保持電圧より高くブレー
クダウン電圧より低い電圧が供給される様な端子
の保護素子として用いた場合、雑音等によつて、
その端子がブレークダウン電圧の16Vより高くな
りかつ負性抵抗領域に入つてしまうと、この端子
に供給されている電圧が保持電圧より高い為、そ
のまま大電流が流れる状態が保持され、ついには
アルミ配線の溶断又は接合の劣化を生じる。 The holding voltage of the conventional example shown in FIG. 4 is higher than the power supply voltage Vcc , as shown in FIG. 6, and is about 8V. For example, when used as a protection element for a terminal to which a voltage higher than the holding voltage and lower than the breakdown voltage is supplied, noise etc.
When that terminal becomes higher than the breakdown voltage of 16V and enters the negative resistance region, the voltage supplied to this terminal is higher than the holding voltage, so a large current continues to flow, and eventually the aluminum Wiring may melt or bonding may deteriorate.
上述した従来の半導体保護装置は、保持電圧が
電源電圧に対しあまり高くないので、保護電圧範
囲が狭いという欠点がある。
The above-described conventional semiconductor protection device has a drawback that the protection voltage range is narrow because the holding voltage is not very high relative to the power supply voltage.
本発明の目的は、保護電圧範囲の広い半導体保
護装置を提供する事にある。 An object of the present invention is to provide a semiconductor protection device with a wide protection voltage range.
本発明の半導体保護装置は、第1の導電型の半
導体基板又は島状領域とその表面上に近接して形
成される二つの第2導電型の拡散層領域とから成
るバイポーラトランジスタを保護素子とする半導
体保護装置において、前記拡散層領域の一方を直
接又は抵抗を介して外部接続端子に接続し、他方
を電源電圧と前記半導体基板・前記島状領域又は
保護されるべき第2の導電型の絶縁ゲート電界効
果トランジスタのソースが接続される電位との間
の電位に接続して構成される。
The semiconductor protection device of the present invention uses, as a protection element, a bipolar transistor consisting of a semiconductor substrate or island-like region of a first conductivity type and two diffusion layer regions of a second conductivity type formed close to each other on the surface thereof. In the semiconductor protection device, one of the diffusion layer regions is connected directly or through a resistor to an external connection terminal, and the other is connected to the power supply voltage and the semiconductor substrate, the island region, or the second conductivity type to be protected. It is connected to a potential between the potential to which the source of the insulated gate field effect transistor is connected.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す断面模形図で
ある。 FIG. 1 is a schematic cross-sectional view showing one embodiment of the present invention.
第1図に示す実施例はP型半導体基板1の表面
にN型拡散層領域2を2箇所設ける事によつて
NPNのバイポーラトランジスタを形成し、一方
のN型拡散層領域2を外部接続端子101に接続
し、P型半導体基板1を接地電位に接続し、他方
のN型拡散層領域2をN型電界効果トランジスタ
(図示せず)のソース電位(通常は接地電位)と
異なる電源電圧端子102に接続して構成されて
いる。 The embodiment shown in FIG. 1 is achieved by providing two N-type diffusion layer regions 2 on the surface of a P-type semiconductor substrate 1.
An NPN bipolar transistor is formed, one N-type diffusion layer region 2 is connected to the external connection terminal 101, the P-type semiconductor substrate 1 is connected to the ground potential, and the other N-type diffusion layer region 2 is connected to the N-type field effect transistor. It is connected to a power supply voltage terminal 102 that is different from the source potential (usually ground potential) of a transistor (not shown).
第2図にその等価回路、第3図にその電圧・電
流特性を示す。第3図において折線aが第1図に
示す実施例の特性であり、折線bは第4図に示す
従来例の特性(第6図における折線bに同じ)で
ある。 Fig. 2 shows its equivalent circuit, and Fig. 3 shows its voltage/current characteristics. In FIG. 3, the broken line a is the characteristic of the embodiment shown in FIG. 1, and the broken line b is the characteristic of the conventional example shown in FIG. 4 (same as the broken line b in FIG. 6).
第3図に図示するように保持電圧はほぼ電源電
圧Vcc(5V)分高くなり、第4図に示す従来例に
おいて8Vだつたものが第1図に示す実施例にお
いては13Vとなる。又、負性抵抗領域に入る電圧
そして電流も大きくなる。 As shown in FIG. 3, the holding voltage is increased by approximately the power supply voltage Vcc (5V), and what was 8V in the conventional example shown in FIG. 4 becomes 13V in the embodiment shown in FIG. Also, the voltage and current entering the negative resistance region also increase.
以上説明したように、第1図に示す実施例は
NPNトランジスタとしてのN型拡散層領域2の
一方を電源電圧端子102に接続する事によつて
保持電圧を高くする事ができ、電源電圧Vccより
高く保持電圧より低い電圧が供給される端子にこ
のNPNトランジスタを保護として用い、この端
子の電位が雑音等によつてブレークダウン電圧を
越えて負性抵抗領域に入つても、その端子の電圧
が元にもどれば、保持電圧より低い為、大電流が
流れ続く事はなく、アルミ配線の溶断又は接合の
劣化等による保護素子の破壊を招かない。 As explained above, the embodiment shown in FIG.
By connecting one side of the N-type diffusion layer region 2 as an NPN transistor to the power supply voltage terminal 102 , the holding voltage can be increased. This NPN transistor is used as protection, and even if the potential of this terminal exceeds the breakdown voltage and enters the negative resistance region due to noise, etc., if the voltage of that terminal returns to its original state, it will be lower than the holding voltage, so The current does not continue to flow, and the protection element will not be destroyed due to melting of the aluminum wiring or deterioration of the bond.
なお、第1図に示す実施例においてはN型拡散
領域2の一方の電位を電源電圧Vccにしているが、
ここの電位はP型半導体基板1の電位(又はN型
電界効果トランジスタのソース電位)より高けれ
ば良くその高くなつた分だけ保持電圧は高くな
る。 In the embodiment shown in FIG. 1, the potential of one side of the N-type diffusion region 2 is set to the power supply voltage Vcc ;
It is sufficient that the potential here is higher than the potential of the P-type semiconductor substrate 1 (or the source potential of the N-type field effect transistor), and the higher the potential, the higher the holding voltage becomes.
また、第1図の実施例における外部接続端子1
01とそれに接続されるN型拡散層領域2の一方
との間に抵抗を設けても同様の効果が得られる。 In addition, the external connection terminal 1 in the embodiment shown in FIG.
A similar effect can be obtained by providing a resistor between 01 and one of the N type diffusion layer regions 2 connected thereto.
以上P型基板を用いる場合について本発明の実
施例を説明したが、Pウエル領域中にN型拡散層
を形成した場合も同じである。 Although the embodiments of the present invention have been described above with respect to the case where a P-type substrate is used, the same applies to the case where an N-type diffusion layer is formed in the P-well region.
以上詳細に説明したように本発明の半導体保護
装置は、半導体基板又は島状領域と異なる導電型
の二つの拡散層領域の一方を半導体基板・島状領
域又は(この拡散層領域と同じ導電型の)電界効
果トランジスタのソースが接続される電位とは異
なる電位に接続する事により、製造工程に何ら工
程を付加する事なく保持電圧を高くでき、したが
つて保護電圧範囲を広くする事ができるという効
果がある。
As explained in detail above, the semiconductor protection device of the present invention can protect one of the two diffusion layer regions of a conductivity type different from the semiconductor substrate or the island region from the semiconductor substrate or the island region or (the same conductivity type as the diffusion layer region). By connecting to a potential different from the potential to which the source of the field effect transistor is connected, the holding voltage can be increased without adding any steps to the manufacturing process, and the protection voltage range can therefore be widened. There is an effect.
第1図は本発明の半導体保護装置の一実施例を
示す断面模型図、第2図・第3図は第1図に示す
実施例の回路図および電圧・電流特性を示すグラ
フ、第4図は従来の半導体保護装置の一例を示す
断面模型図、第5図・第6図は第4図に示す従来
例の回路図および電圧・電流特性を示すグラフで
ある。
1……P型半導体基板、2……N型拡散層領
域、101……外部接続端子、102……電源電
圧端子。
Fig. 1 is a cross-sectional model diagram showing one embodiment of the semiconductor protection device of the present invention, Figs. 2 and 3 are a circuit diagram and a graph showing voltage/current characteristics of the embodiment shown in Fig. 1, and Fig. 4 5 is a cross-sectional model diagram showing an example of a conventional semiconductor protection device, and FIGS. 5 and 6 are a circuit diagram and a graph showing voltage/current characteristics of the conventional example shown in FIG. 4. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type diffusion layer region, 101... External connection terminal, 102... Power supply voltage terminal.
Claims (1)
の表面上に近接して形成される二つの第2導電型
の拡散層領域とから成るバイポーラトランジスタ
を保護素子とする半導体保護装置において、 前記拡散層領域の一方を直接又は抵抗を介して
外部接続端子に接続し、他方を電源電圧と前記半
導体基板・前記島状領域又は保護されるべき第2
の導電型の絶縁ゲート電界効果トランジスタのソ
ースが接続される電位との間の電位に接続した事
を特徴とする半導体保護装置。[Claims] 1. A bipolar transistor consisting of a semiconductor substrate or island region of a first conductivity type and two diffusion layer regions of a second conductivity type formed close to each other on the surface thereof is used as a protection element. In the semiconductor protection device, one of the diffusion layer regions is connected to an external connection terminal directly or through a resistor, and the other is connected to a power supply voltage and the semiconductor substrate, the island region, or the second region to be protected.
A semiconductor protection device characterized in that the source of an insulated gate field effect transistor of conductivity type is connected to a potential between that and the potential to which it is connected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60141714A JPS622656A (en) | 1985-06-28 | 1985-06-28 | Semiconductor protecting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60141714A JPS622656A (en) | 1985-06-28 | 1985-06-28 | Semiconductor protecting device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS622656A JPS622656A (en) | 1987-01-08 |
JPH0528493B2 true JPH0528493B2 (en) | 1993-04-26 |
Family
ID=15298488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60141714A Granted JPS622656A (en) | 1985-06-28 | 1985-06-28 | Semiconductor protecting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS622656A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58173866A (en) * | 1982-04-06 | 1983-10-12 | Citizen Watch Co Ltd | Protective circuit |
-
1985
- 1985-06-28 JP JP60141714A patent/JPS622656A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58173866A (en) * | 1982-04-06 | 1983-10-12 | Citizen Watch Co Ltd | Protective circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS622656A (en) | 1987-01-08 |
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