JPS62264716A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To attain sure setting or resetting by connecting emitters in common of data storage transistors (TR) via a resistor. CONSTITUTION:Emitters of a TR Q4 connected to a set input S and a TR Q1 connected to a reset input R are connected in common, and its connecting point and the emitters of data storage TRs Q2, Q3 are connected respectively via resistors R5, R6. Through the constitution above, in impressing a high level to the reset input R, since a bias higher by a potential difference of the resistor R6 is impressed to the base-emitter junction, the TR Q1 is easily turned on more than the data storage TR Q3 and sure resetting is attained. When a high level is given to the set input S, sure setting is impressed by the same reason as above.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-flop circuit that operates upon input of set and reset signals.

[Prior art] Conventional current-switching logic circuit IC-structured flip-flop circuits with a set or reset input of kW are widely used in digital computers, etc., and are mainly used as basic logic circuits for multiplication circuit devices. are doing. As a typical example of the prior art, a circuit configuration as shown in FIG. 3 is well known. A reset input transistor Q1 is connected to this f'L.
and a data holding transistor Q2゜Q from the collector of each set input transistor Q4, through feedback emitter follower transistors Qs and Q6t, and further through level shift resistors R5 and R6k.
3, forming an R8 flip-flop as a whole. Here, resistors R5, R, The pace potential of F transistors Q2 and Q3 is level-shifted.

As another conventional example, as shown in FIG.
A BS flip-flop is connected to the Vcc side common contact of R2 and to the power supply Vcc through a resistor R5, which level-shifts the entire circuit in response to set and reset inputs to ensure its operation. be.

[Problem that the invention seeks to solve]

The conventional R8 flip-flop circuit described above with a resistor inserted in the feedback path has the disadvantage that the frequency characteristics deteriorate because the resistor is inserted in series with the base of the transistor that controls the entire frequency characteristics of the 7 flip-flop. be. ′!
In addition, a device in which the overall level is shifted by a resistor has the disadvantage that the output logic level shifts from the normal level, resulting in an insufficient logic range.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-flop circuit that improves the drawbacks of the conventional circuits and is capable of stable set and reset operations without affecting frequency characteristics, output levels, etc.

Means for Solving All Problems C] In the flip-flop circuit of the present invention, a current switching type logic circuit is provided using a transistor for inputting a set signal or a reset signal, and a data holding transistor whose emitters are commonly connected. In the flip-flop circuit 11, which alternately writes and holds F data by switching the current path, the emitters of the data holding transistors are commonly connected through all the resistors. do.

〔Example〕

Next, the present invention will be explained with reference to all the drawings.

The first factor is a circuit diagram showing an embodiment of the present invention.

Transistors Ql and Q4 have their emitters connected in common,
Reset and set signals are input to each pace.

A data holding transistor Q21 whose emitters are commonly connected to this common emitter point via resistors R5 and R, respectively.
Qs't"-1 whose respective collectors are connected to transistors Q
1 and the collectors of Q4, respectively, and the respective collector connection points are connected to the emitter follower transistors Qs and Q4.
outputs Q and Q are obtained through s', and feedback is provided to the bases of the data holding transistors Q2 and Q3;
Furthermore, the emitters of transistors Q5゜Q6 and the power supply vIII
The configuration is such that n resistors R3 and R4 are connected between each of them. -Now, reset input R, set manual power S
Assuming that both are at low level, output Q is at high level, and output Q is at low level. L, level shift transistor Q
5゜Q6 output Q is high level, output Q is low level, resistor R6 usually has a potential difference of 50 to 100 m between both ends.
Set it so that it becomes V.

Next, for example, if we consider the case where a high level is applied to the reset input f', the potential of the reset input competes with the high level of the pace potential of the transistor Q3, but the potential of the reset input competes with the high level of the pace potential of the transistor Q1. I:
Since the bias voltage is applied to as many ports as the potential difference of the resistor R6, if we think about it excessively, the data holding transistor Q3x') is also turned on, and the reset can be done reliably.

Next, even if a high level is applied only to the set human power S, this circuit can be considered in the same way as above because the set input and reset input are symmetrical, and the voltage across the resistor R5 is reliable. It becomes possible to apply cellar lt- to.

In this embodiment, unlike the conventional S flip-flop circuit shown in FIGS. 3 and 4, since no resistor is inserted in the signal feedback route, there is no deterioration in frequency characteristics, and there is no level shift on the Vcc side. Since the output logic level does not shift or decrease, a normal output logic level is ensured, and the internal data retention level is maintained to ensure reliable set or reset operation. .

FIG. 2 is a circuit diagram showing another embodiment of the present invention. This example is an embodiment of the present invention in a flip-flop computer with a general master-slave type chair set.

That is, in order to integrate the clock input and the data input, an engineered zero signal is applied to the transistor Q11, which is at a lower logic level, and the write state of the data input applied to the transistor Q3FC and the write state of the data input applied to the transistor Q4. Since the D flip-flop operation is performed by alternately switching the data holding state by Qs, the emitter of transistor Q7, which applies the reset signal, is level-shifted from the emitters of transistors Q4 and Qs by resistors Rs and Rs. Although it is connected to a point, its basic operation and effect,
This is exactly the same as that shown in FIG. 1, and a reliable reset operation is obtained.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, in a flip-flop circuit having a set or reset signal input, the level is shifted from each emitter of the data holding transistor to the intersection point by a resistor, and the set or reset signal is input to the emitter of the transistor for manual input. By connecting these, it is possible to improve the problems of conventional technology such as deterioration of constant frequency characteristics, shift of output logic level, and reduction of field of view, and realize a flip-flop circuit that can perform simple set or reset operations. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of conventional RS flip-flop circuits. R, 8, D, C... Signal input, Q, Q
...Output, VCC, Vllll-...Power supply,
Qx~Q19...Transistor, R1'=R1
1...Resistor, Il~Mechanical 2...Constant current source, VRI, VB2...Reference voltage source.

Claims (1)

[Claims] It is configured to include a transistor for inputting a set signal or a reset signal, and a current switching type logic circuit using a transistor for data retention whose emitters are connected in common, and it alternately writes and retains data by switching the current path. 1. A flip-flop circuit characterized in that the emitters of the data holding transistors are commonly connected via a resistor.