JPH0233207A - Buffer circuit - Google Patents

Abstract

PURPOSE:To attain low distortion by cancelling the nonlinearity of a base- emitter voltage of a transistor(TR) by means of a local feedback. CONSTITUTION:Since a collector current IC1 (IC2) of a TR Q1 (Q2) and a collector current IC3 (IC4) of a TR Q3 (Q4) are made equal by the local feedback of a current mirror circuit 4(5), the base-emitter voltage of the TRs Q1 (Q2) and Q3 (Q4) is made equal. Thus, even when the collector current IC1 (IC2) of the TR Q1 (Q2) is changed by IL/2 each by a load current IL and the base-emitter voltage Vbe1 (Vbe2) is nonlinearly varied, since the base-emitter voltage Vbe3 (Vbe4) is varied to cancel the nonlinear change, the potential at the emitter of the TR Q1 (Q2) and the base of the TR Q3 (Q4) are equal. As a result, the components giving effect onto the gain are resistors R1, R2 only and since they have no nonlinear characteristic, the linearity and the harmonic wave distortion characteristic are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION A. OBJECTS OF THE INVENTION [Field of Industrial Application] The present invention relates to improving the DC and AC operating characteristics of a buffer circuit.

[Conventional technology]

Conventionally, a diamond circuit shown in FIG. 8 has been used as a low distortion buffer circuit. @Input voltage V ill to child 1
, bias resistors R1 to R4 and transistor Q
Voltage VfLlt is output from terminal 6 via a two-stage emitter follower circuit composed of Q1 to Q4. 7 and 8 are constant current sources that supply current to the first stage emitter follower.

[Problem to be solved by the invention]

However, in the above circuit, due to the load current I, transistor Q1. When a current change of approximately TL/2 occurs in Q2, correspondingly transistors Q+ and Q
Since the base-emitter voltage Vbe of No. 2 changes nonlinearly, nonlinearity of gain and harmonic distortion occur.

Although the above two phenomena were suppressed to some extent by the canceling effect of the transistor (h, Q2), it was not sufficient.

The present invention has been made to solve the above problems,
The purpose of this invention is to realize a buffer circuit with low distortion.

``Structure of the Invention'' [Means for Solving the Problems] A buffer circuit according to the present invention includes a first transistor to which a voltage based on an input voltage is applied to the base terminal, and a base terminal to the emitter terminal of the first transistor. and a current mirror circuit that feeds back the collector current of the second transistor to the emitter current of the first transistor, and the emitter follower output of the second transistor corresponds to the input voltage. It is characterized by being configured to do so.

[Effect]

Because the current mirror circuit makes the collector current of the second transistor equal to the emitter current of the first transistor, the base-emitter voltages of the first transistor and the second transistor are always equal, and nonlinearity is canceled out. Ru.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of a buffer circuit according to the present invention. Below, the symbols in parentheses indicate the circuit symbols on the negative side. 1 is the input terminal, R3 (R4) is a resistor for determining the bias current whose one end is connected to this input terminal 1, and 2
(3) is a constant current source of current I whose one end is connected to the other end of the resistor R3 (R4) and the other end is connected to the positive power supply Vcc (negative power supply VEE), and Q3 (Qa) is the emitter of the first stage.・
A first transistor of the PNP type (NPN type), Q+ (Q2), which constitutes a follower and whose base terminal is connected to the other end of the resistor R3 (R4) and whose collector terminal is connected to the negative power supply VEE (positive power supply Vcc) constitutes a second-stage emitter follower, whose base terminal is connected to the transistor Q:+(Qa
), the second transistor of NPN type (PNP type) is connected to the emitter terminal of the transistor Q+ (Q2
) by inputting the collector current of transistor Q3 (Qa).
The first (second) current mirror circuit, R1 (R2), outputs to the emitter terminal of the transistor Q (Q2) to determine the bias current that the emitter terminal of the transistor Q (Q2) is connected to one end and the other end is connected to the terminal 6. resistance.

2 to 4 show specific examples of the first current mirror circuit 4, which is composed of PNP transistors, but the second current mirror circuit 5 is constructed using NPN transistors. The I-plane terminal of the current mirror circuit shown in Fig. 2 should be configured with transistor Q+<
Q2), and its I01+1 terminal is connected to the emitter terminal of transistor Q3 (Qa). In FIGS. 2 and 3, the input/output current ratio Iaut/Inn is 1, and in FIG. 4 it is 1/n.

The operation of the buffer circuit configured as described above will be explained next. Local feedback of current mirror circuit 4(5) causes transistors Q1. Q3 (Q2, Qa
) is considered small and ignored, Q+(Q2
) and the collector current IC3 (Ic4) of Q3 (Qa>) are equal, so the base-emitter voltages of transistors Q (Q2) and Qa (Qa) are equal. That is, Vbe2=Vbe4+ Vbe2=Vbe4...
(1) This relationship is based on the change in base-emitter voltage ΔVbe++
The same holds true for ΔVbe3+ΔVba2+ΔVbe4, so the load current IL causes the transistor Q
The collector current Ic+(Ic2) of l(Q2) is I L
/ 2, the base-emitter voltage Vbe +
Even if (Vbe2) changes nonlinearly, the base-emitter voltage Vbe: + (Vbea) changes to offset this, so the emitter terminal of transistor (h (Q2)) and the base of transistor Q3 (Qa) The potentials of the terminals become equal.As a result, the only parts that affect the gain are the resistors R1 and R2, which have no nonlinearity, so linearity and harmonic distortion characteristics are greatly improved.Note that transistors Q1 to Bias current Tc of Q4, ~IC4 is resistor R
Determined by 1 to R4 and current source 2.3, R1=R2, R
)=Ra, Ic + =IC2=IC3=ICa = (R3/R
＋ )■ ・・・(
2).

According to the buffer circuit having such a configuration, by canceling out the nonlinearity of the base-emitter voltage of the transistor by local feedback, it is possible to improve the linearity of the gain in DC (direct current) operation and to improve the gain linearity in AC (alternating current) operation. It is possible to reduce harmonic distortion during operation.

Note that although the above embodiment shows a case where the current ratio of the first and second stage transistors is 1:1, the power consumption of the first stage can be reduced by setting the current ratio to 1:n. Can be done. For this purpose, for example, the circuit shown in FIG. 4 may be used as a current mirror circuit.

FIG. 5 shows a second embodiment of the buffer circuit according to the present invention,
FIG. 7 is a configuration circuit diagram showing another configuration in which the current ratio between first-stage and second-stage transistors is 1:n.

The same parts as in FIG. 1 are given the same symbols and the explanation is omitted. As the current mirror circuit 4.5, one of the type shown in FIG. 2 is used. The difference from FIG. 1 is that the second stage transistor Q1. The point is that a plurality of emitter follower circuits each including a plurality of transistors Qp+ to QP/2TL-2 whose collector terminals are connected to a power supply and a plurality of resistors RP and RP/2TL-2 are connected in parallel with Q2. The resistor Ri that connects the current mirror input terminals is a resistor for starting transistors Q and Q4, and is used when the power is turned on, when the input signal swings out of the allowable range, and when transistor Q1 (Q2) is turned off. This also prevents Q3 (Q4) from turning off and becoming inoperable. A constant current necessary to turn on the transistor Q:+ (Q4) flows through the resistor Ri through the current mirror circuit 4 within a range that does not interfere with the principle operation.

The other operations are the same as those shown in FIG. 1, so their explanation will be omitted. Note that in FIG. 1, the circuit for starting the transistor is omitted.

FIG. 6 shows a third embodiment of the buffer circuit according to the present invention,
FIG. 3 is a configuration circuit diagram showing a configuration in which the number of parts is approximately halved.

The same parts as in FIG. 1 are given the same symbols and explanations are omitted. 6 Also, Q+, Q, and the starting circuit are omitted. The operation is similar to that of the positive side circuit in FIG. 1 except that the bias current is determined by the constant current source 7. In this configuration, the symmetry of the rise and fall of a large-amplitude waveform in high-speed operation is slightly sacrificed, but the configuration becomes simpler.

FIG. 7 shows a fourth embodiment of the buffer circuit according to the present invention,
FIG. 2 is a configuration circuit diagram showing an example in which the input impedance is increased by FET (field effect transistor) input. The same parts as in FIG. 1 are given the same symbols and the explanation is omitted.

Different from FIG. 1, the constant current source 2 is omitted, the resistor R4 becomes 0, F E Ta2 and the resistor) constitute a source follower circuit, and the voltage V applied to the gate of F E' iTL changes the base voltage of transistor Q3.Q-.

Constant current sources 1j+ and Ij2 are each connected to transistor Q3.
Connect the emitter terminals of Q- in opposite directions to flow a current, and connect the transistors Q1 to Q4 in the same way as RL in Figure 5.
Configure the startup circuit. Each constant current source 'L3+Iid is a transistor Q.

Connect the collector terminals of Q2 in opposite directions to 7” Q
+ → R1 → R2 → Q2 → 8, and constant current source I
It completely compensates for the slight effect that t++I12 has on the base-emitter voltage cancellation behavior. Diode DI
(D2) is provided to provide a current path for Ij3 (1, 4) when transistor Q (Q2) is turned off, and is turned off during normal operation. The operation of the pond is similar to that in FIG.

C. Effects of the Invention j As is clear from the above description, the present invention achieves lower distortion, that is, improved linearity of gain in DC operation, and
A buffer circuit in which harmonic distortion is reduced in C operation can be realized with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of a buffer circuit according to the present invention, FIGS. 2 to 4 are partial circuit diagrams showing specific configuration examples of the current mirror circuit in the circuit in FIG. 1,
FIG. 5 is a configuration circuit diagram showing a second embodiment of the buffer circuit according to the present invention, FIG. 6 is a configuration block diagram showing a third embodiment of the buffer circuit according to the present invention, and FIG. 7 is a configuration circuit diagram showing a third embodiment of the buffer circuit according to the present invention. A configuration block diagram showing a fourth embodiment of a buffer circuit according to
FIG. 8 is a circuit diagram showing a conventional example of a buffer circuit.

Claims (1)

[Claims] a first transistor to which a voltage based on the input voltage is applied to the base terminal; a second transistor whose base terminal is connected to the emitter terminal of the first transistor;
a current mirror circuit that feeds back the collector current of the transistor to the emitter current of the first transistor, and is configured such that the emitter follower output of the second transistor corresponds to the input voltage. .