JPH04278611A - Constant current circuit - Google Patents
Constant current circuitInfo
- Publication number
- JPH04278611A JPH04278611A JP3041489A JP4148991A JPH04278611A JP H04278611 A JPH04278611 A JP H04278611A JP 3041489 A JP3041489 A JP 3041489A JP 4148991 A JP4148991 A JP 4148991A JP H04278611 A JPH04278611 A JP H04278611A
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- JP
- Japan
- Prior art keywords
- current
- transistor
- circuit
- collector
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
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- Amplifiers (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、定電流回路に関し、特
に正・負の２電源で使用する回路に適した定電流回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current circuit, and more particularly to a constant current circuit suitable for use with two positive and negative power supplies.
【０００２】0002
【従来の技術】従来、定電流回路を構成する際には、図
４に示す様に、基準電圧源２をオペアンプ１０の非反転
入力に接続し、このオペアンプ１０の出力をトランジス
タ５のベースに接続し、トランジスタ５のエミッタから
オペアンプ１０の反転入力に接続し、この接続点より抵
抗７を介して基準電圧源１に接続し、トランジスタ５の
コレクタをカレントミラー回路９の電流入力に接続し、
カレントミラー回路８の電流出力を出力端８とする構成
としていた。Conventionally, when constructing a constant current circuit, as shown in FIG. The emitter of the transistor 5 is connected to the inverting input of the operational amplifier 10, the connection point is connected to the reference voltage source 1 via the resistor 7, the collector of the transistor 5 is connected to the current input of the current mirror circuit 9,
The configuration is such that the current output of the current mirror circuit 8 is used as the output terminal 8.
【０００３】このような構成により、トランジスタ５の
エミッタ電位はオペアンプ１０で全帰還した増幅器を構
成し、オペアンプ１０を非反転入力の電位である基準電
圧源２と同電位となる。With this configuration, the emitter potential of the transistor 5 constitutes an amplifier in which the operational amplifier 10 is fully fed back, and the operational amplifier 10 has the same potential as the reference voltage source 2, which is the potential of the non-inverting input.
【０００４】その為、抵抗７（Ｒ）には基準電圧源１と
基準電圧源２の電位との差電圧（Ｖ）が加わる。Therefore, a difference voltage (V) between the potentials of the reference voltage source 1 and the reference voltage source 2 is applied to the resistor 7 (R).
【０００５】その結果、トランジスタ５のエミッタ電流
ＩＥは、ＩＥ＝Ｖ／Ｒとなり、カレントミラー回路９の
入力電流は、トランジスタ５のコレクタ電流ＩＣで、Ｉ
Ｃ＝αＩＥ（α：トランジスタ５のベース接地時の電流
増幅率）カレントミラー回路９の電流出力には、トラン
ジスタ５のコレクタ電流ＩＣと同一レベルの電流（ＩＯ
）が吸込まれる。従って、As a result, the emitter current IE of the transistor 5 becomes IE=V/R, and the input current of the current mirror circuit 9 is the collector current IC of the transistor 5, which is IE=V/R.
C=αIE (α: current amplification factor when the base of transistor 5 is grounded) The current output of the current mirror circuit 9 has a current (IO
) is absorbed. Therefore,
【０００６】ＩＯ＝ＩＣ＝αＩＥ＝α・Ｖ／Ｒとなる。IO=IC=αIE=α·V/R.
【０００７】[0007]
【発明が解決しようとする課題】上述した従来の定電流
回路は、トランジスタ５の介している為、トランジスタ
５のベース電流分だけエミッタ電流よりコレクタ電流が
低下する。In the conventional constant current circuit described above, since the transistor 5 is used, the collector current is lower than the emitter current by the base current of the transistor 5.
【０００８】その結果、カレント・ミラー回路９の電流
入力がトランジスタ５のベース電流分低下する上、トラ
ンジスタ５のベース接地時の電流増幅率が温特等で変化
した時、出力端８の電流出力が変わる欠点がある。As a result, the current input to the current mirror circuit 9 decreases by the base current of the transistor 5, and when the current amplification factor when the base of the transistor 5 is grounded changes due to temperature characteristics, the current output at the output terminal 8 decreases by the amount of the base current of the transistor 5. There are drawbacks that change.
【０００９】又、従来の定電流回路は、オペアンプ１０
とトランジスタ５と抵抗７とカレントミラー回路９で構
成されている為、多くの回路部品で構成され集積回路化
した時、ペレットサイズが大きくなる欠点がある。[0009] Also, the conventional constant current circuit has an operational amplifier 10
Since it is composed of a transistor 5, a resistor 7, and a current mirror circuit 9, it has a drawback that the pellet size becomes large when it is composed of many circuit parts and integrated into an integrated circuit.
【００１０】本発明の目的は、安定した電流出力が得ら
れ、回路部品の削減が計れる定電流回路を提供すること
にある。An object of the present invention is to provide a constant current circuit that can provide stable current output and reduce the number of circuit components.
【００１１】[0011]
【課題を解決するための手段】本発明の定電流回路は、
基準電圧源２とトランジスタ４のエミッタに接続し、ト
ランジスタ４のベースとトランジスタ５のベース・コレ
クタとトランジスタ６のエミッタに接続し、トランジス
タ６のコレクタをカレントミラー回路９の電流入力に接
続し、該カレントミラー回路の第１の電流出力を前記ト
ランジスタ４のコレクタ６のベースに接続し、前記トラ
ンジスタ５のエミッタと基準電圧源１間に抵抗７を挿入
し、前記カレントミラー回路９の第１の電流出力と並列
に少なくとも１つの以上電流出力を有している。[Means for Solving the Problems] The constant current circuit of the present invention has the following features:
The reference voltage source 2 is connected to the emitter of the transistor 4, the base of the transistor 4 is connected to the base/collector of the transistor 5, and the emitter of the transistor 6, and the collector of the transistor 6 is connected to the current input of the current mirror circuit 9. A first current output of the current mirror circuit is connected to the base of the collector 6 of the transistor 4, a resistor 7 is inserted between the emitter of the transistor 5 and the reference voltage source 1, and the first current output of the current mirror circuit 9 is connected to the base of the collector 6 of the transistor 4. It has at least one current output in parallel with the output.
【００１２】0012
【実施例】次に、本発明について図面を用いて説明する
。図１は本発明を示す回路図、図２は、図１のより具体
的に示した回路図である。図２に示すように、正負の２
電源で使用した定電流回路で、基準電圧源（ＧＮＤ）１
７をＰＮＰトランジスタ４のエミッタと抵抗１８を介し
てＮＰＮトランジスタ２０のベースとダイオード１９の
アノードを接続し、ＰＮＰトランジスタ４のベースをＰ
ＮＰトランジスタ５のベース・コレクタのＰＮＰトラン
ジスタ６のエミッタに接続し、ＰＮＰトランジスタのコ
レクタをＰＮＰトランジスタ６のベースとＮＰＮトラン
ジスタ２０，１１のコレクタに接続し、ＰＮＰトランジ
スタ６のコレクタをＮＰＮトランジスタ１４のベースと
ＮＰＮトランジスタ１２のコレクタに接続し、ＮＰＮト
ランジスタ１４のエミッタをＮＰＮトランジスタ１１，
１２，１３のベースに接続し、ＮＰＮトランジスタ１１
，１２，１３の各エミッタと基準電圧源３（負電源）間
に各抵抗１５，１６，１７を挿入する。[Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing the present invention, and FIG. 2 is a circuit diagram showing FIG. 1 more specifically. As shown in Figure 2, positive and negative 2
Constant current circuit used in power supply, reference voltage source (GND) 1
7 is connected to the emitter of the PNP transistor 4 and the base of the NPN transistor 20 and the anode of the diode 19 via the resistor 18, and the base of the PNP transistor 4 is connected to the
The base and collector of the NP transistor 5 are connected to the emitter of the PNP transistor 6, the collector of the PNP transistor is connected to the base of the PNP transistor 6 and the collectors of the NPN transistors 20 and 11, and the collector of the PNP transistor 6 is connected to the base of the NPN transistor 14. is connected to the collector of the NPN transistor 12, and the emitter of the NPN transistor 14 is connected to the NPN transistor 11,
12 and 13, and the NPN transistor 11
, 12, 13 and the reference voltage source 3 (negative power supply).
【００１３】ＰＮＰトランジスタ５のエミッタから抵抗
７を介して基準電圧源１（正電源）に接続し、ＮＰＮト
ランジスタ１４のコレクタも基準電圧源１（正電源）に
接続する。ダイオード１９のカソードは基準電圧源３（
負電源）に接続し、ＮＰＮトランジスタ１３のコレクタ
は定電流出力の出力端７に接続する構成である。The emitter of the PNP transistor 5 is connected to the reference voltage source 1 (positive power source) via the resistor 7, and the collector of the NPN transistor 14 is also connected to the reference voltage source 1 (positive power source). The cathode of the diode 19 is connected to the reference voltage source 3 (
The collector of the NPN transistor 13 is connected to the constant current output terminal 7.
【００１４】次に動作の説明する。ＰＮＰトランジスタ
５のエミッタ電流ＩＥ５は、Ｖ１を基準電源１の電圧、
Ｖ１７を基準電圧源１７、Ｒ７を抵抗７とすると、ＩＥ
５＝（Ｖ１−Ｖ１７）／Ｒ７
となる。ＰＮＰトランジスタ６のエミッタ電流ＩＥ６は
、Next, the operation will be explained. The emitter current IE5 of the PNP transistor 5 has V1 as the voltage of the reference power supply 1,
If V17 is the reference voltage source 17 and R7 is the resistor 7, IE
5=(V1-V17)/R7. The emitter current IE6 of the PNP transistor 6 is
【００１５】ＩＥ６＝ＩＥ５＋ＩＢ４ （ＩＢ４；Ｐ
ＮＰトランジスタ４のベース電流）となり、ＰＮＰトラ
ンジスタ６のコレクタ電流ＩＣ６は、ＩＣ６＝ＩＥ５＋
ＩＢ４−ＩＢ６ （ＩＢ６；ＰＮＰトランジスタ６の
ベース電流）となる。IE6=IE5+IB4 (IB4;P
The base current of the NP transistor 4), and the collector current IC6 of the PNP transistor 6 is IC6=IE5+
IB4-IB6 (IB6; base current of PNP transistor 6).
【００１６】ＰＮＰトランジスタ４，５，６が同一トラ
ンジスタで同一電流増幅率の時、
ＩＣ６＝ＩＥ５＝（Ｖ１−Ｖ１７）／Ｒ７と成り、ＮＰ
Ｎトランジスタ１１，１２，１３，１４と抵抗１５，１
６，１７から成るカレント・ミラー回路９の電流入力と
なる。When PNP transistors 4, 5, and 6 are the same transistors and have the same current amplification factor, IC6=IE5=(V1-V17)/R7, and the NP
N transistors 11, 12, 13, 14 and resistors 15, 1
This serves as a current input to a current mirror circuit 9 consisting of 6 and 17.
【００１７】カレント・ミラー回路９に電流ロスがない
時、出力端８（ＮＰＮトランジスタ１３のコレクタ電流
）よりＩＣ６の電流が吸込まれる。When there is no current loss in the current mirror circuit 9, the current of the IC 6 is sucked from the output terminal 8 (collector current of the NPN transistor 13).
【００１８】抵抗１８とＮＰＮトランジスタ２０とダイ
オード１９は、基準電圧源１，基準電圧源３がオンした
時、ＰＮＰトランジスタ６，５がオンする為のスタート
アップ回路である。The resistor 18, the NPN transistor 20, and the diode 19 are a start-up circuit for turning on the PNP transistors 6 and 5 when the reference voltage source 1 and the reference voltage source 3 are turned on.
【００１９】ＰＮＰトランジスタ４，５，６からなるカ
レント・ミラー回路をＰＮＰトランジスタ４，５，６，
２１のウィルソンカレントミラー回路で構成した実施例
を図３に記す。A current mirror circuit consisting of PNP transistors 4, 5, 6,
An example constructed of 21 Wilson current mirror circuits is shown in FIG.
【００２０】[0020]
【発明の効果】以上説明した様に、本発明はトランジス
タ５と整合のとれたトランジスタ４，６を用いる事で、
従来抵抗７に加わる電圧と抵抗７で決定するカレントミ
ラー回路の電流出力がトランジスタ５のベース電流分低
下する事を防止し、トランジスタ５のベース接地時の電
流増幅率の変化による影響も無くし設定通りの安定な電
流出力を得る事ができる。[Effects of the Invention] As explained above, the present invention uses transistors 4 and 6 that are matched with transistor 5.
Conventionally, the current output of the current mirror circuit determined by the voltage applied to the resistor 7 and the resistor 7 is prevented from decreasing by the base current of the transistor 5, and the influence of changes in the current amplification factor when the base of the transistor 5 is grounded is eliminated, so that the current output is determined by the resistor 7. A stable current output can be obtained.
【００２１】又、大幅な回路部品の削減が計られ、非常
に集積回路に適した定電流回路が提供できる。Furthermore, the number of circuit components can be significantly reduced, and a constant current circuit that is highly suitable for integrated circuits can be provided.
【図１】本発明の定電流回路を示す回路図である。FIG. 1 is a circuit diagram showing a constant current circuit of the present invention.
【図２】本発明の具体的実施例を示す回路図である。FIG. 2 is a circuit diagram showing a specific embodiment of the present invention.
【図３】本発明の他の具体的実施例を示す回路図である
。FIG. 3 is a circuit diagram showing another specific embodiment of the present invention.
【図４】従来用いられている定電流回路を示す回路図で
ある。FIG. 4 is a circuit diagram showing a conventionally used constant current circuit.
１ 基準電圧源１
２，１７ 基準電圧源
３ 基準電圧源
４，５，６，２１ ＰＮＰトランジスタ１１，１
２，１３，１４，２０ ＮＰＮトランジスタ７，
１５，１６，１７，１８ 抵抗１９ ダイ
オード
９ カレント・ミラー回路
１０ オペアンプ1 Reference voltage source 1 2, 17 Reference voltage source 3 Reference voltage source 4, 5, 6, 21 PNP transistor 11, 1
2, 13, 14, 20 NPN transistor 7,
15, 16, 17, 18 Resistor 19 Diode 9 Current mirror circuit 10 Operational amplifier
Claims (2)
タのエミッタに接続し、前記第１のトランジスタのベー
スと第２のトランジスタのベース・コレクタと第３のト
ランジスタのエミッタに接続し、前記第３のトランジス
タのコレクタをカレントミラー回路の電流入力に接続し
、前記カレントミラー回路の第１の電流出力を前記第１
のトランジスタのコレクタと第３のトランジスタのベー
スに接続し、前記第２のトランジスタのエミッタと第２
の基準電圧源間に抵抗を挿入して電流供給源とし、前記
カレントミラー回路の第１の電流出力と並列に少くとも
１つの以上の電流出力を備える事を特徴とする定電流回
路。1. A first reference voltage source is connected to an emitter of a first transistor, a base of the first transistor, a base-collector of a second transistor, and an emitter of a third transistor; The collector of the third transistor is connected to the current input of the current mirror circuit, and the first current output of the current mirror circuit is connected to the first current output of the current mirror circuit.
is connected to the collector of the transistor and the base of the third transistor, and the emitter of the second transistor and the second
A constant current circuit, characterized in that a resistor is inserted between the reference voltage sources of the current mirror circuit as a current supply source, and at least one current output is provided in parallel with the first current output of the current mirror circuit.
コレクタに接続されコレクタが前記カレントミラー回路
の第１の電流出力に接続されベースが前記第１のコレク
タと前記第３のトランジスタのベースに接続されたこと
を特徴とする請求項１記載の定電流回路。2. An emitter is connected to a collector of the first transistor, a collector is connected to a first current output of the current mirror circuit, and a base is connected to the first collector and the base of the third transistor. The constant current circuit according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3041489A JP2710473B2 (en) | 1991-03-07 | 1991-03-07 | Constant current circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3041489A JP2710473B2 (en) | 1991-03-07 | 1991-03-07 | Constant current circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04278611A true JPH04278611A (en) | 1992-10-05 |
| JP2710473B2 JP2710473B2 (en) | 1998-02-10 |
Family
ID=12609768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3041489A Expired - Fee Related JP2710473B2 (en) | 1991-03-07 | 1991-03-07 | Constant current circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2710473B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001154748A (en) * | 1999-09-14 | 2001-06-08 | Toshiba Microelectronics Corp | Constant current source |
| US6535790B2 (en) | 2000-02-21 | 2003-03-18 | Kanazawa Institute Of Technology | Automated library system with retrieving and respositing robot |
-
1991
- 1991-03-07 JP JP3041489A patent/JP2710473B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001154748A (en) * | 1999-09-14 | 2001-06-08 | Toshiba Microelectronics Corp | Constant current source |
| US6535790B2 (en) | 2000-02-21 | 2003-03-18 | Kanazawa Institute Of Technology | Automated library system with retrieving and respositing robot |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2710473B2 (en) | 1998-02-10 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970924 |
|
| LAPS | Cancellation because of no payment of annual fees |