JPH0423509A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To operate the flip-flop circuit by a low power supply voltage and to prevent an output data signal from generating noise by constituting this flip-flop circuit without using any series gate. CONSTITUTION:The flip-flop circuit is composed of a data holding circuit and a control circuit. This data holding circuit is composed of a pair of transistors Q5 and Q7 whose base and collector are connected to each other, and load resistors R4-R6 connected to the respective collectors, and this control circuit is composed of transistors Q3, Q4, Q8 and Q9 connected so as to constitute a current switching circuit together with the transistors Q5 and Q7. Since the flip-flop circuit is constituted without using any series gate and a differential signal is not used as a clock signal, any phase difference is not generated in the clock signal. Thus, the flip-flop circuit can be obtained to be operatable by the low power supply voltage without generating noise in the output data signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-flop circuit, and particularly to a flip-flop circuit that can operate at a low power supply voltage. [Prior Art] Recently, due to the decrease in element breakdown voltage due to the increase in the integration of LSIs,
There is an increasing demand for circuits that can operate at low power supply voltages. Against this background, low power supply voltage (~3V)
An ECL type flip-flop circuit that can operate in the following manner has been proposed (described in Japanese Patent Laid-Open No. 63-220615). The operation of this prior art will be explained below. FIG. 2(a) is a circuit diagram of a conventional example, and FIG. 2(b) shows the potential relationship of input signals of the circuit. This flip-flop circuit is composed of two current switching circuits. That is,
1 - transistor Q101. ．． A first current switching circuit consisting of transistor Q102 and transistor Q105. This is a second current switching circuit consisting of Q106. The input data signal D' is input to the first current switching circuit, and the second current switching circuit receives the input data signal D'.
The output data signals Q and Q' of the flip-flop circuit are input to the current switching circuit. In the same figure, D', Q
, Q' and CLK, CLK' represent signals having opposite polarities, that is, differential signals. In this technique, the first current switching circuit and the second current switching circuit are switched using differential clock signals CLK and CLK'. Therefore, when the tarlock signal CLK is at a high potential and CLK' is at a low potential, the transistor Q103 becomes non-conductive, and at the same time the first current switching circuit is activated, the transistor Q107 becomes conductive. The second current switching circuit is deactivated. As a result, the output data signals Q and Q' are switched according to the input data signals D and D'. On the other hand, when the clock signal CLK is at a low potential and CLK' is at a high potential, the transistor Q103 becomes conductive, the first current switching circuit is inactivated, and at the same time, the 1-transistor Q107 becomes non-conductive. state, and the second current switching circuit is activated. This allows the input data signal to
Even if D'' changes, the output data signals Q and Q' do not switch, and the data is retained.The above operation performs the function of the flip-flop circuit.As described above, this conventional example According to the invention, since the function of a flip-flop circuit can be realized without using a series gate, it is possible to operate with a power supply voltage of about 3V, and it is possible to provide a flip-flop circuit suitable for lowering the power supply voltage. However, in the prior art shown in FIG. 2, the clock signals CLK,
When the phase of CLK' shifts, there is a problem in that noise occurs in the output data signal. That is, Fig. 2(c)
As shown in , when the clock signals CLK and CLK' are out of phase, both CLK and CLK' have a higher potential than the input data signal D during the period Δt, so the transistors QIO3 and Q107 become conductive at the same time. , the first and second current switching circuits are simultaneously deactivated. As a result, current no longer flows through the load resistors RIOI and RIOI, causing noise in the output data signals Q and Q', causing the primary stage logic gate to malfunction. The object of the present invention is to be able to operate with a low power supply voltage, and
An object of the present invention is to provide a flip-flop circuit in which noise does not occur in an output data signal. [Means for Solving the Problems] The above object is to provide a flip-flop circuit, a pair of transistors whose bases and collectors are connected to each other directly or via an emitter follower, and a pair of transistors connected to the respective collectors of the pair of transistors. This can be achieved by comprising a load element and a control circuit that supplies current to either of the emitters of the pair of transistors according to the input data signal and clock signal. [Operation] The flip-flop circuit of the present invention is constructed without using a series gate, as in the prior art. Furthermore, a differential signal is not required as a clock signal. Therefore, no phase difference occurs in the clock signal, and no noise occurs in the output data signal. Thereby, it is possible to provide a flip-flop circuit that can operate with a low power supply voltage and does not generate noise in the output data signal. [Example] The present invention will be described in detail below. FIG. 1 shows a first embodiment of the present invention. The circuit of this example has a base and a collector connected to each other.
Pair of transistors Q5. Q7 (in the figure, the base and collector are connected directly, but they may be connected via an emitter follower), a data holding circuit consisting of load resistors R4, R5, and R6 connected to the respective collectors, and a transistor Q5. ．． Q3. connected to Q7 to form a current switching circuit. Q4 and Q8. It consists of a control circuit consisting of Q9. The data holding circuit uses the lock signal CL
When K'' is at a high potential, the control circuit operates to hold the information of the input data signal, D'
and Q5. according to the clock signal CLK'. It works to supply current to either Ql. Now, consider the case where the clock signal CLK' is at a low potential (data reading state), the input data signal is at a high potential, and D' is at a low potential. Here, each input signal CLK', D,
D' and transistor Q5 in the data holding circuit. It is assumed that the potential relationship between the collector nodes c and c' of Q7 is set as shown in FIG. 4(b). When CLK' becomes a low potential, from the potential relationship shown in FIG. Q7 becomes conductive. Therefore, the output data signal Q changes to high potential, Q' changes to low potential, the collector node Q' in the data holding circuit changes to low potential, and C changes to high potential. As a result, the same data as the input data signal is output, and at the same time, the data is held in the data holding circuit. On the other hand, when CLK'' becomes a high potential (data retention state),
Since the high potential of CLK' is set between the potentials of c and c', transistors 1 to Q4. , Ql become conductive, Q outputs a high potential, and Q' outputs a low potential. This output state remains 1 even if the input data signal D' changes.
- Since transistor Q4 continues to be conductive, it does not change and the data is held. The above operation shows that the present technology can realize the function of a flip-flop circuit. As described above, according to this embodiment, a flip-flop circuit can be realized without using a series gate.
It can operate with a power supply voltage of about 3V. Moreover, since a differential signal is not required as a clock signal, no phase difference occurs in the clock signal, and noise can be prevented from occurring in the output data signal. FIG. 3 shows a second embodiment of the present invention.
This is an embodiment in which set/reset functions 1 to 1 are added to the embodiment shown in the figure. The circuit configuration is I-transistor Q1.3. The embodiment is the same as the embodiment shown in FIG. 1 except that Ql4 is added. When setting data to this flip-flop circuit,
The data set signal S is driven to a potential higher than the potential of the collector node C'' in the data holding circuit.
Transistor Q5 becomes non-conductive, C goes to high potential,
Q' changes to a low potential. Therefore, the output data signal Q is at a high potential, Q' is at a low potential, and data is set. To reset the data, use the data reset signal R.
is driven to a higher potential than the collector node C in the data holding circuit. As a result, transistors 1 to Q7 become non-conductive, C changes to a low potential, and Q' changes to a high potential. Therefore, the output data signal Q is at a low potential, and Q' is at a high potential, and the data is reset. As described above, according to this embodiment, it is possible to realize a flip-flop circuit with a set/reset function that can operate at a low power supply voltage. Effects of the Invention 1 As described above, according to the present invention, a flip-flop circuit can be realized without using a series gate, so that it can be operated with a power supply voltage of about 3 µ. Moreover, since a differential signal is not required as a clock signal, no phase difference occurs in the clock signal, and noise can be prevented from occurring in the output data signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram and signal potential relationship diagram showing the first embodiment of the present invention, FIG. 2 is a circuit diagram and signal potential relationship diagram showing the prior art, and FIG. 3 is a diagram showing the signal potential relationship according to the present invention. FIG. 2 is a circuit diagram showing a second embodiment. Explanation of symbols Q1 to Q14. , Ql, 01-Q112...1-transistor, R1-R9, RIOI-R106... resistor,
D, D'... Input data signal, Q, Q'... Output data signal, CLK, CLK'... Clock Shintan

Claims (1)

[Claims] 1. A pair of transistors whose bases and collectors are connected to each other directly or via an emitter follower, a load element connected to the collector of each of the pair of transistors, and an input data signal and a clock signal. A flip-flop circuit comprising a control circuit that supplies current to either of the emitters of the pair of transistors in accordance with the above. 2. First and second transistors whose emitters are commonly connected to one emitter of the pair of transistors, and third and fourth transistors whose emitters are commonly connected to the emitter of the other of the pair of transistors. The control circuit is configured with two current sources respectively connected to the common connection point of the two emitters, and a differential input data signal is supplied to the bases of the first and third transistors, and the second and fourth transistors are connected to each other. 2. The flip-flop circuit according to claim 1, wherein a clock signal is applied to the base of the transistor.