JPS62261156A - 導電性バイア経路の形成方法 - Google Patents

導電性バイア経路の形成方法

Info

Publication number
JPS62261156A
JPS62261156A JP62074598A JP7459887A JPS62261156A JP S62261156 A JPS62261156 A JP S62261156A JP 62074598 A JP62074598 A JP 62074598A JP 7459887 A JP7459887 A JP 7459887A JP S62261156 A JPS62261156 A JP S62261156A
Authority
JP
Japan
Prior art keywords
level
layer
metal
dielectric layer
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62074598A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0569308B2 (enExample
Inventor
ドニス・ジョージ・フラジェロ
ヤヌスズ・スタニスロウ・ウイルクジンスキー
デービッド・フランク・ウィットマン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS62261156A publication Critical patent/JPS62261156A/ja
Publication of JPH0569308B2 publication Critical patent/JPH0569308B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP62074598A 1986-04-30 1987-03-30 導電性バイア経路の形成方法 Granted JPS62261156A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85727586A 1986-04-30 1986-04-30
US857275 1986-04-30

Publications (2)

Publication Number Publication Date
JPS62261156A true JPS62261156A (ja) 1987-11-13
JPH0569308B2 JPH0569308B2 (enExample) 1993-09-30

Family

ID=25325615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62074598A Granted JPS62261156A (ja) 1986-04-30 1987-03-30 導電性バイア経路の形成方法

Country Status (3)

Country Link
EP (1) EP0243707B1 (enExample)
JP (1) JPS62261156A (enExample)
DE (1) DE3784961D1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4122362A1 (de) * 1991-07-05 1993-01-14 Siemens Ag Anordnung und verfahren zum kontaktieren von leitenden schichten
JP2601640B2 (ja) * 1993-01-19 1997-04-16 ヒューズ・エアクラフト・カンパニー 電気的導体構造を作成する方法と大規模集積回路
FR2784502B1 (fr) * 1998-10-09 2002-08-30 St Microelectronics Sa Structures d'interconnexion de circuits integres
KR102142795B1 (ko) * 2016-02-02 2020-09-14 도쿄엘렉트론가부시키가이샤 선택적 증착을 이용한 금속 및 비아의 자기 정렬

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220952A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
DE3234907A1 (de) * 1982-09-21 1984-03-22 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten schaltung
JPS59126671A (ja) * 1983-01-10 1984-07-21 Mitsubishi Electric Corp 半導体装置
DE3407799A1 (de) * 1984-03-02 1985-09-05 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren zur herstellung einer multilayer-hybridschaltung
US4640010A (en) * 1985-04-29 1987-02-03 Advanced Micro Devices, Inc. Method of making a package utilizing a self-aligning photoexposure process

Also Published As

Publication number Publication date
JPH0569308B2 (enExample) 1993-09-30
EP0243707A2 (en) 1987-11-04
DE3784961D1 (de) 1993-04-29
EP0243707B1 (en) 1993-03-24
EP0243707A3 (en) 1990-07-11

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