DE3784961D1 - Verfahren zur herstellung einer verbindungsleitung. - Google Patents

Verfahren zur herstellung einer verbindungsleitung.

Info

Publication number
DE3784961D1
DE3784961D1 DE8787104806T DE3784961T DE3784961D1 DE 3784961 D1 DE3784961 D1 DE 3784961D1 DE 8787104806 T DE8787104806 T DE 8787104806T DE 3784961 T DE3784961 T DE 3784961T DE 3784961 D1 DE3784961 D1 DE 3784961D1
Authority
DE
Germany
Prior art keywords
producing
connection line
connection
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787104806T
Other languages
English (en)
Inventor
Donis George Flagello
Janusz Stanislaw Wilczynski
David Frank Witman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3784961D1 publication Critical patent/DE3784961D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8787104806T 1986-04-30 1987-04-01 Verfahren zur herstellung einer verbindungsleitung. Expired - Lifetime DE3784961D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US85727586A 1986-04-30 1986-04-30

Publications (1)

Publication Number Publication Date
DE3784961D1 true DE3784961D1 (de) 1993-04-29

Family

ID=25325615

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787104806T Expired - Lifetime DE3784961D1 (de) 1986-04-30 1987-04-01 Verfahren zur herstellung einer verbindungsleitung.

Country Status (3)

Country Link
EP (1) EP0243707B1 (de)
JP (1) JPS62261156A (de)
DE (1) DE3784961D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4122362A1 (de) * 1991-07-05 1993-01-14 Siemens Ag Anordnung und verfahren zum kontaktieren von leitenden schichten
GB2281659B (en) * 1993-01-19 1996-07-03 Hughes Aircraft Co Off-chip conductor structure and fabrication method for large intergrated microcircuits
FR2784502B1 (fr) * 1998-10-09 2002-08-30 St Microelectronics Sa Structures d'interconnexion de circuits integres
SG11201806578XA (en) * 2016-02-02 2018-09-27 Tokyo Electron Ltd Self-alignment of metal and via using selective deposition

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220952A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
DE3234907A1 (de) * 1982-09-21 1984-03-22 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten schaltung
JPS59126671A (ja) * 1983-01-10 1984-07-21 Mitsubishi Electric Corp 半導体装置
DE3407799A1 (de) * 1984-03-02 1985-09-05 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren zur herstellung einer multilayer-hybridschaltung
US4640010A (en) * 1985-04-29 1987-02-03 Advanced Micro Devices, Inc. Method of making a package utilizing a self-aligning photoexposure process

Also Published As

Publication number Publication date
EP0243707A3 (en) 1990-07-11
JPS62261156A (ja) 1987-11-13
JPH0569308B2 (de) 1993-09-30
EP0243707A2 (de) 1987-11-04
EP0243707B1 (de) 1993-03-24

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Legal Events

Date Code Title Description
8332 No legal effect for de