JPS62261114A - Laminated ceramic capacitor and manufacture of the same - Google Patents
Laminated ceramic capacitor and manufacture of the sameInfo
- Publication number
- JPS62261114A JPS62261114A JP10591386A JP10591386A JPS62261114A JP S62261114 A JPS62261114 A JP S62261114A JP 10591386 A JP10591386 A JP 10591386A JP 10591386 A JP10591386 A JP 10591386A JP S62261114 A JPS62261114 A JP S62261114A
- Authority
- JP
- Japan
- Prior art keywords
- sheet
- ceramic capacitor
- multilayer ceramic
- capacitance adjustment
- electrode pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 5
- 239000011230 binding agent Substances 0.000 claims description 4
- 238000007606 doctor blade method Methods 0.000 claims description 4
- 238000004898 kneading Methods 0.000 claims description 4
- 239000000843 powder Substances 0.000 claims description 4
- 238000007650 screen-printing Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000007689 inspection Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は積層セラミックコンデンサおよびその製造方法
に関し、特にコンデンサ素子の表面部分に形成する容量
調整用電極の構造並びにその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same, and more particularly to the structure of a capacitance adjusting electrode formed on the surface portion of a capacitor element and the method for manufacturing the same.
一般に、従来の容量調整用電極を有する積層セラミック
コンデンサは第5図乃至第8図の工程により形成される
。まず、第5図に示すように1放細化したセラミック粉
末と有機バインダを混練した後、ドクターブレード法に
よって生シートを作製する。次にこのシートを所望の面
積に切断し、その表面の片面にスクリーン印刷により内
部電極11を被着・乾燥した生シート1と、容量調整用
電極12を被着・乾燥した生シート7とを用意する。次
に内部電極11を印刷した生シート1を、電極を印刷し
ない生シフトからなる保護層2で上下をはさむように、
所望の枚数を積み重ねた後、最上層に容量調整用電極1
2を形成した生シート7を同様に積み重ね第6図に示す
ように積層体8を形成し熱圧着した後、個片状態に切断
して第7図(a)〜(c)に示すような積層した生チツ
プ個片9を形成する。第7図(a)〜(c)において、
第7図(a)は生チツプ個片の斜視図、第7図(b)は
第7図(a)のd−d’断面図、第7図(c)はe−e
’断面図である。この生チツプ個片9を焼成し、両端に
端子電極5を焼き付けて第8図に示すような容量調整用
電極を有する積層セラミックコンデンサ20を作製する
。Generally, a conventional multilayer ceramic capacitor having capacitance adjusting electrodes is formed by the steps shown in FIGS. 5 to 8. First, as shown in FIG. 5, after kneading a finely sized ceramic powder and an organic binder, a green sheet is produced by a doctor blade method. Next, this sheet is cut into a desired area, and a raw sheet 1 with internal electrodes 11 coated and dried by screen printing on one side of the surface, and a raw sheet 7 with capacitance adjustment electrodes 12 coated and dried. prepare. Next, the raw sheet 1 on which the internal electrodes 11 are printed is sandwiched between the top and bottom of the protective layer 2 made of raw shift without printing the electrodes.
After stacking the desired number of sheets, capacitance adjustment electrode 1 is placed on the top layer.
The raw sheets 7 formed with 2 are stacked in the same way to form a laminate 8 as shown in FIG. 6, which is bonded under heat and then cut into individual pieces as shown in FIGS. 7(a) to (c). Laminated raw chip pieces 9 are formed. In FIGS. 7(a) to (c),
Fig. 7(a) is a perspective view of an individual raw chip, Fig. 7(b) is a sectional view taken along dd' of Fig. 7(a), and Fig. 7(c) is a sectional view taken along ee-e.
'This is a cross-sectional view. This green chip piece 9 is fired, and terminal electrodes 5 are baked on both ends to produce a multilayer ceramic capacitor 20 having capacitance adjusting electrodes as shown in FIG.
上述した容量調整用電極を有する積層セラミックコンデ
ンサ20は、容量調整用電極12が表面に出ているため
、その製造工程中の検査工程において第9図に示すよう
に検査端子13と容量調整用電極12の位置関係が悪い
と、端子電極5と容量調整用電極12間で短絡してしま
い検査不能となる。また、第10図に示すように、実装
時に容量調整用電極12が印刷配線基板15のランド1
4で短絡するため、容量調整用電極12は、容量調整用
積層セラミックコンデンサ20の片面にしか設定できず
、実装時に容量調整用電極12が上向きになるように配
慮せねばならないという欠点がある。In the multilayer ceramic capacitor 20 having the capacitance adjustment electrode described above, since the capacitance adjustment electrode 12 is exposed on the surface, the test terminal 13 and the capacitance adjustment electrode are separated from each other during the inspection process in the manufacturing process as shown in FIG. If the positional relationship between the electrodes 12 is poor, a short circuit will occur between the terminal electrode 5 and the capacitance adjustment electrode 12, making inspection impossible. Further, as shown in FIG. 10, when the capacitance adjustment electrode 12 is mounted on the land 1 of the printed wiring board 15,
4, the capacitance adjustment electrode 12 can only be set on one side of the capacitance adjustment multilayer ceramic capacitor 20, and care must be taken to ensure that the capacitance adjustment electrode 12 faces upward during mounting.
本発明の目的は、製造工程中での効率よい検査が可能で
あり、容量調整用電極を容量調整用積層セラミックコン
デンサの上下両面に配設でき、また実装時において一面
に配設した場合でも容量調整用電極を上向きになるよう
配慮する必要がなく実装コストを下げられる積層セラミ
ックコンデンサおよびその製造方法を提供することにあ
る。The purpose of the present invention is to enable efficient inspection during the manufacturing process, to enable capacitance adjustment electrodes to be disposed on both the upper and lower surfaces of a multilayer ceramic capacitor for capacitance adjustment, and to enable capacitance adjustment even when disposed on one surface during mounting. It is an object of the present invention to provide a multilayer ceramic capacitor and a method for manufacturing the same, which can reduce mounting costs without the need to take care that adjustment electrodes face upward.
本発明の第1の発明の積層セラミックコンデンサは、内
部電極パターンを設けた生シートを一枚以上積み重ねた
第゛の生シートと、前記第1の生シートの上下に保護絶
縁層のみからなる第2の生シートを積層した積層セラミ
ックコンデンサ素子の最外層表面下近傍に、容量調整用
の電極パターンを少なくとも1個設けることにより構成
される。The multilayer ceramic capacitor according to the first aspect of the present invention includes a first raw sheet formed by stacking one or more raw sheets provided with internal electrode patterns, and a second raw sheet consisting of only protective insulating layers above and below the first raw sheet. The present invention is constructed by providing at least one electrode pattern for capacitance adjustment near the bottom of the outermost layer surface of a multilayer ceramic capacitor element in which green sheets of No. 2 are laminated.
また、本発明の第2の発明の積層セラミックコンデンサ
の製造方法は、微細化したセラミック粉末と有機バイン
ダを混練しドクターブレード法により生シー1〜を形成
する工程と、前記生シートの一方の面にスクリーン印刷
による内部電極パターンを有する内部電極用シー1−と
容量調整用の電極パターンを有する容量調整用シートと
を形成する工程と、前記内部電極用シートを中心に配し
て上下に保護層となる生シートを配した後、前記容量調
整用シートを配する工程と、さらに上保護層を最外層に
配する工程とを含んで構成される。Further, the method for manufacturing a multilayer ceramic capacitor according to the second aspect of the present invention includes the steps of kneading fine ceramic powder and an organic binder and forming a green sheet 1 through a doctor blade method, and one side of the green sheet. A step of forming an internal electrode sheet 1- having an internal electrode pattern by screen printing and a capacitance adjustment sheet having an electrode pattern for capacitance adjustment, and forming protective layers on top and bottom of the internal electrode sheet with the internal electrode sheet in the center. After arranging the green sheet, the method includes the step of arranging the capacity adjusting sheet, and the step of further arranging an upper protective layer as the outermost layer.
次に、本発明の実施例について図面を参照して説明する
。第1図乃至第4図は本発明の一実施例の構造並びに製
造方法を説明するために工程順に示した斜視図並びに断
面図である。Next, embodiments of the present invention will be described with reference to the drawings. 1 to 4 are perspective views and cross-sectional views shown in order of steps to explain the structure and manufacturing method of one embodiment of the present invention.
まず、第1図に示すように、微細化したセラミック粉末
と有機バインダを混練した後、ドクターブレード法によ
って生シートを作製する。次にこの生シートを所望の面
積に切断し、その表面の片面にスクリーン印刷により内
部電極11を被着・乾燥した・生シー?−1と、容量調
整用電極12を被着・乾燥した生シート7とを用意する
。次に内部電極11を印刷した生シート1を、電極を印
刷しない生シー1−からなる保護層2で上下をはさむよ
うに、所望の枚数を績み重ねた後、内部電極12を被着
・乾燥した生シー1へ7を同様に積み重ね、さらに上保
護層6を焼成後の厚さ10μm〜50μrnとなるよう
に所望枚数最外層に積み重ねて、第2図に示すような積
層体3を形成し熱圧着する。First, as shown in FIG. 1, after kneading fine ceramic powder and an organic binder, a green sheet is produced by a doctor blade method. Next, this green sheet was cut into a desired area, and internal electrodes 11 were applied to one side of the surface by screen printing and dried. -1 and a raw sheet 7 on which the capacitance adjusting electrode 12 is adhered and dried are prepared. Next, the desired number of raw sheets 1 with internal electrodes 11 printed on them are sandwiched between upper and lower protective layers 2 made of raw sheets 1- with no electrodes printed on them, and then the internal electrodes 12 are applied. 7 is similarly stacked on the dried green sheet 1, and a desired number of upper protective layers 6 are stacked on the outermost layer so that the thickness after firing is 10 μm to 50 μrn, to form a laminate 3 as shown in FIG. Then heat and press.
次に、第3図(a、)〜(c)に示すように、個片状態
に切断して積層した生チツプ個片4を形成する。なお、
第3図(a)は生チツプ個片の斜視図、第3図(b)は
第3図(a>のb−b’線の断面図、第3図(c)はc
−c′線の断面図である。Next, as shown in FIGS. 3(a) to 3(c), individual raw chips 4 are formed by cutting into individual pieces and stacking them. In addition,
Fig. 3(a) is a perspective view of an individual raw chip, Fig. 3(b) is a sectional view taken along line bb' of Fig. 3(a>), and Fig. 3(c) is a
It is a sectional view taken along the line -c'.
次に、この生チツプ個片4を焼成し、両端に端子電極5
を焼き付けると本発明の積層セラミックコンデンサ10
が完成する。Next, this raw chip piece 4 is fired, and terminal electrodes 5 are attached to both ends.
When baked, the multilayer ceramic capacitor 10 of the present invention
is completed.
しかるときは、内部電極パターン11を設けた生シート
を一枚以上積み重ねた第1の生シート1と、第1の生シ
ート1の上下に保護絶縁層からなる第2の生シート2を
積層した積層セラミックコンデンサ素子の最外層表面下
近傍に容量調整用の電極パターンを少なくとも1個設け
た積層セラミ・ツクコンデンサが得られる。In such a case, a first raw sheet 1 made by stacking one or more raw sheets provided with internal electrode patterns 11 and a second raw sheet 2 made of a protective insulating layer are laminated above and below the first raw sheet 1. A multilayer ceramic capacitor is obtained in which at least one electrode pattern for capacitance adjustment is provided near the surface of the outermost layer of a multilayer ceramic capacitor element.
なお、本容量調整用積層セラミックコンデンサ10にお
いて主保護層が50μmより厚いと、レーザーなどによ
り容量調整用電極12をトリミングするときのエネルギ
ーが大きすぎ、誘電体を変質させ絶縁抵抗の低下がみら
れる。また10μmより薄いと、生シートの成形、収り
扱いが困難となり製造上の問題が発生する。In addition, if the main protective layer in the multilayer ceramic capacitor 10 for capacitance adjustment is thicker than 50 μm, the energy used when trimming the capacitance adjustment electrode 12 using a laser or the like is too large, causing the dielectric to change in quality and resulting in a decrease in insulation resistance. . Moreover, if it is thinner than 10 μm, it becomes difficult to form and handle the raw sheet, causing manufacturing problems.
以上、説明したように本発明は容量調整用電極の上に薄
い所定厚さの誘電体を設けることにより、従来の積層セ
ラミックコンデンサと同様の方法で、その製造工程中で
の効率良い検査が可能であり、容量調整用電極を容量調
整用積層セラミックコンデンサの上下両面に配設できる
。このため、実装時に基板のランドでショートすること
をさけるために容量調整用電極を上向きになるよう配慮
する必要がなく、実装コストを下げることができるとい
う効果がある。As explained above, by providing a thin dielectric material of a predetermined thickness on the capacitance adjustment electrode, the present invention enables efficient inspection during the manufacturing process in the same manner as conventional multilayer ceramic capacitors. Therefore, the capacitance adjustment electrodes can be disposed on both the upper and lower surfaces of the capacitance adjustment multilayer ceramic capacitor. For this reason, there is no need to take care that the capacitance adjustment electrode faces upward in order to avoid short-circuiting at the land of the board during mounting, which has the effect of reducing mounting costs.
第1図乃至第4図は本発明の一実施例の構造並びに製造
方法を説明するために工程順に示した斜視図並びに断面
図であり、第1図は熱圧着時の積層構造を示す分解斜視
図、第2図は第1図の熱圧着後の積層体のa−a′線断
面図、第3図(a)〜(c)は第2図の破線で分離した
生チツプ個片の斜視図とそのb−b’線及びc−c’線
の各断面図、第4図は第3図(a)〜(C)の両端に端
子電極を形成した積層セラミックコンデンサの斜視図、
第5図乃至第8図は従来の積層セラミックコンデンサの
構造並びにその製造方法を説明するために工程順に示し
た斜視図並びに断面図、第9図は従来の積層セラミック
コンデンサの一例の検査工程における検査端子と容量調
整用電極の位置関係を示す断面図、第10図は従来の積
層セラミックを印刷配線基板に実装したとき容量調整電
極と印刷配線基板のランドの位置関係を示す断面図であ
る。
1・・・生シート、2・・・保護層、3.8・・・積層
体、4.9・・・生チツプ個片、5・・・端子電極、6
・・・主保護層、1り、20・・・積層セラミックコン
デンサ、7・・・容量調整用電極生シート、11・・・
内部電極、12・・・容量調整用電極、13・・・検査
端子、14・・・ランド、15・・・印刷配線基板。
:(理人弁理士内原 晋
イ)1呈; 1 m
処2 図
捲5図
第6図
第8 図
第9図
卿ル1フ線基・仮
寿10 図1 to 4 are perspective views and cross-sectional views shown in the order of steps to explain the structure and manufacturing method of one embodiment of the present invention, and FIG. 1 is an exploded perspective view showing the laminated structure during thermocompression bonding. Figures 2 and 2 are cross-sectional views taken along line a-a' of the laminate shown in Figure 1 after thermocompression bonding, and Figures 3 (a) to (c) are perspective views of individual green chips separated along the broken lines in Figure 2. Fig. 4 is a perspective view of a multilayer ceramic capacitor with terminal electrodes formed at both ends as shown in Figs. 3(a) to (C);
5 to 8 are perspective views and cross-sectional views shown in order of steps to explain the structure of a conventional multilayer ceramic capacitor and its manufacturing method, and FIG. 9 is an example of an inspection process of a conventional multilayer ceramic capacitor. FIG. 10 is a cross-sectional view showing the positional relationship between the terminal and the capacitance adjusting electrode, and FIG. 10 is a cross-sectional view showing the positional relationship between the capacitance adjusting electrode and the land of the printed wiring board when a conventional multilayer ceramic is mounted on the printed wiring board. DESCRIPTION OF SYMBOLS 1... Raw sheet, 2... Protective layer, 3.8... Laminated body, 4.9... Raw chip piece, 5... Terminal electrode, 6
... Main protective layer, 1, 20 ... Multilayer ceramic capacitor, 7 ... Electrode raw sheet for capacitance adjustment, 11 ...
Internal electrode, 12... Capacity adjustment electrode, 13... Inspection terminal, 14... Land, 15... Printed wiring board. : (Patent Attorney Susumu Uchihara) 1 Presentation; 1 m Place 2 Figure 5 Figure 6 Figure 8 Figure 9
Claims (3)
み重ねた第1の生シートと、前記第1の生シートの上下
に保護絶縁層のみからなる第2の生シートを積層した積
層セラミックコンデンサ素子の最外層表面下近傍に、容
量調整用の電極パターンを少なくとも1個設けたことを
特徴とする積層セラミックコンデンサ。(1) A multilayer ceramic capacitor in which a first green sheet is a stack of one or more green sheets provided with an internal electrode pattern, and a second green sheet consisting of only a protective insulating layer is laminated above and below the first green sheet. A multilayer ceramic capacitor characterized in that at least one electrode pattern for capacitance adjustment is provided near the bottom of the surface of the outermost layer of the element.
極パターン間の距離が10μm以上50μ以下である特
許請求の範囲第(1)項記載の積層セラミックコンデサ
。(2) The multilayer ceramic capacitor according to claim (1), wherein the distance between the surface of the outermost layer and the electrode pattern for capacitance adjustment near the bottom of the surface of the outermost layer is 10 μm or more and 50 μm or less.
しドクターブレード法により生シートを形成する工程と
、前記生シートの一方の面にスクリーン印刷による内部
電極パターンを有する内部電極用シートと容量調整用の
電極パターンを有する容量調整用シートとを形成する工
程と、前記内部電極用シートを中心に配して上下に保護
層となる生シートを配した後、前記容量調整用シートを
配する工程と、さらに上保護層を最外層に配する工程と
を含むことを特徴とする積層セラミックコンデンサの製
造方法。(3) A step of kneading fine ceramic powder and an organic binder to form a raw sheet using a doctor blade method, and a sheet for internal electrodes having an internal electrode pattern by screen printing on one side of the raw sheet, and a sheet for capacity adjustment. A step of forming a capacitance adjustment sheet having an electrode pattern of A method for manufacturing a multilayer ceramic capacitor, further comprising the step of disposing an upper protective layer as the outermost layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10591386A JPS62261114A (en) | 1986-05-08 | 1986-05-08 | Laminated ceramic capacitor and manufacture of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10591386A JPS62261114A (en) | 1986-05-08 | 1986-05-08 | Laminated ceramic capacitor and manufacture of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62261114A true JPS62261114A (en) | 1987-11-13 |
Family
ID=14420101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10591386A Pending JPS62261114A (en) | 1986-05-08 | 1986-05-08 | Laminated ceramic capacitor and manufacture of the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62261114A (en) |
-
1986
- 1986-05-08 JP JP10591386A patent/JPS62261114A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0285873B1 (en) | Method of producing a multi-layered ceramic capacitor | |
JPH06112100A (en) | Manufacture of electronic part | |
JP2000340448A (en) | Laminated ceramic capacitor | |
JP2742414B2 (en) | Manufacturing method of multilayer ceramic electronic component | |
JPH1126291A (en) | Chip capacitor array | |
JPS6235257B2 (en) | ||
JP2000269074A (en) | Multilayer ceramic capacitor and manufacture thereof | |
JPH06204075A (en) | Stacked ceramic electronic component for high frequency and its manufacture | |
JPH1116776A (en) | Capacitor array | |
JPS62261114A (en) | Laminated ceramic capacitor and manufacture of the same | |
JP3642462B2 (en) | Manufacturing method of laminated parts | |
JPH06314630A (en) | Ceramic-lamination electronic component | |
JPS60124813A (en) | Method of producing laminated ceramic capacitor | |
JPH0750462A (en) | Electronic circuit board | |
JPS6373514A (en) | Laminated ceramic capacitor and manufacture of the same | |
JPH0515295B2 (en) | ||
JPH084053B2 (en) | Monolithic ceramic capacitors | |
JPS6092604A (en) | Laminated ceramic condenser and method of producing same | |
JPH01262695A (en) | Ceramic multilayer board having built-in capacitor | |
JPH0590754A (en) | Production of multilayer circuit board | |
JPS58131727A (en) | Method of producing laminated porcelain capacitor | |
JPS6058605A (en) | Laminated ceramic condenser and method of producing same | |
JPS6151815A (en) | Method of producing laminated ceramic condenser | |
JPH1116778A (en) | Capacitor array and its manufacture | |
JPS62252126A (en) | Laminated ceramic capacitor and manufacture of the same |