JPH01262695A - Ceramic multilayer board having built-in capacitor - Google Patents

Ceramic multilayer board having built-in capacitor

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Publication number
JPH01262695A
JPH01262695A JP63092065A JP9206588A JPH01262695A JP H01262695 A JPH01262695 A JP H01262695A JP 63092065 A JP63092065 A JP 63092065A JP 9206588 A JP9206588 A JP 9206588A JP H01262695 A JPH01262695 A JP H01262695A
Authority
JP
Japan
Prior art keywords
dielectric
layer
dielectric layer
built
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63092065A
Other languages
Japanese (ja)
Inventor
Tatsuo Achinami
阿知波 達雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63092065A priority Critical patent/JPH01262695A/en
Publication of JPH01262695A publication Critical patent/JPH01262695A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable capacitor elements to have high dielectric constant, by interposing a specified intermediate layers between an insulator layers having conductor patterns and a dielectric layer having conductor patterns so that capacitor elements are contained internally. CONSTITUTION:Internal electrodes 3 are formed within a dielectric layer 21 consisting of a dielectric and insulator layers 22 consisting of an insulating material are formed on the opposite sides of the dielectric layer 21. External electrodes 13 are formed on the external face of each of the insulator layers 22 and connected with the internal electrodes 3 by means of internal interconnections 23 through the dielectric layer 21, intermediate layers 24 and the insulator layers 22. The intermediate layers 24 are formed of a dielectric material having low reactivity with respect to the insulator layers 22, a content different from the dielectric layer 21, and thermal shrinkage property intermediate between those of the insulator layer 22 and the dielectric layer 21. The capacitor elements thus produced are allowed to have a high dielectric constant.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、コンデンサ素子を内蔵したセラミック多層基
板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ceramic multilayer substrate incorporating a capacitor element.

〔従来の技術〕[Conventional technology]

従来、この種のコンデンサ素子を内蔵したセラミック多
層基板は、例えば第5図に示すように、高誘電率を発現
する誘電体!21内に内部電極3を形成し、誘電体層2
1の両件面に配設された絶縁体層22の外部に形成され
た外部電極13との間を内部配線23により接続した構
造となっていた。
Conventionally, ceramic multilayer substrates with built-in capacitor elements of this type have been made of dielectric materials that exhibit a high dielectric constant, for example, as shown in FIG. An internal electrode 3 is formed within the dielectric layer 21.
The structure was such that an insulator layer 22 disposed on both sides of the device 1 was connected to an external electrode 13 formed on the outside by an internal wiring 23.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のコンデンサ素子内蔵多層基板においては
、絶縁体層22の絶縁性セラミック材料(以下絶縁材と
いう)が誘電体層21の誘電性セラミック(以下誘電材
という)中へ拡散して反応する。また、焼成過程におけ
る絶縁材と誘電材との熱収縮特性が異なるために絶縁体
層と誘電体層との界面で応力、が発生し、両者の剥離、
及び材料内の亀裂が発生する。これらの原因により本来
誘電材が示すべき比誘電率(約10000>に比べて、
著しく劣る比誘電率(約1500)を示し、さらに絶縁
体層と誘電体層との間で導通不良が起こりやすい。従っ
て、大容量のコンデンサを内蔵させるには大面積が必要
となるが、これはコンデンサ素子内蔵セラミック多層基
板の特徴である小型化、高集積化を妨げるばかりでなく
、大面積化することにより絶縁体層と誘電体層との整合
がより難しくなるという欠点がある。
In the conventional multilayer substrate with a built-in capacitor element described above, the insulating ceramic material of the insulating layer 22 (hereinafter referred to as an insulating material) diffuses into the dielectric ceramic material of the dielectric layer 21 (hereinafter referred to as a dielectric material) and reacts therewith. In addition, due to the difference in thermal shrinkage characteristics between the insulating material and the dielectric material during the firing process, stress is generated at the interface between the insulating layer and the dielectric layer, resulting in peeling of the two.
and cracks in the material occur. Due to these reasons, the dielectric constant (approximately 10,000>
It exhibits a significantly poor dielectric constant (approximately 1500), and furthermore, poor conduction is likely to occur between the insulator layer and the dielectric layer. Therefore, a large area is required to incorporate a large-capacity capacitor, but this not only hinders the miniaturization and high integration that are the characteristics of ceramic multilayer boards with built-in capacitor elements, but also increases insulation by increasing the area. The disadvantage is that alignment of the body and dielectric layers becomes more difficult.

本発明の目的は、誘電材と絶縁材とで生じる拡散の遮蔽
、及び両者の熱収縮特性の違いに起因する誘電材と絶縁
材との界面で発生する応力を緩和することができ、誘電
材の本来有している高い比誘電率をセラミック多層基板
内のコンデンサに発現させることが出来るコンデンサ素
子内蔵セラミック多層基板を提供することにある。
The purpose of the present invention is to shield the diffusion caused by the dielectric material and the insulating material, and to alleviate the stress generated at the interface between the dielectric material and the insulating material due to the difference in thermal shrinkage characteristics between the two. An object of the present invention is to provide a ceramic multilayer substrate with a built-in capacitor element, which allows a capacitor within the ceramic multilayer substrate to exhibit the high dielectric constant that it originally has.

〔課題を解決するための手段、〕[Means to solve problems,]

本発明のコンデンサ素子内蔵セラミック多層基板は、導
体パターンが形成された複数の絶縁体層の間に、導体パ
ターンが形成された誘電体層が挟持されたコンデンサ素
子内蔵セラミック多層基板において、前記絶縁体層と前
記誘電体層との間に、絶縁体層と反応性が低く熱収縮特
性が誘電体層と絶縁体層との間にあり、かつ前記誘電体
層とは組成が異なる誘電材料からなる中間層が挟持され
ることを特徴として構成される。
A ceramic multilayer board with a built-in capacitor element of the present invention is a ceramic multilayer board with a built-in capacitor element in which a dielectric layer on which a conductor pattern is formed is sandwiched between a plurality of insulator layers on which a conductor pattern is formed. between the dielectric layer and the dielectric layer, the dielectric material has low reactivity with the insulating layer, has heat shrinkage characteristics between the dielectric layer and the insulating layer, and has a composition different from that of the dielectric layer. The structure is characterized in that the intermediate layer is sandwiched.

なお、前記誘電材料からなる中間層としては、マンガン
・ニオブ酸鉛、マグネシウム・タングステン酸鉛、チタ
ン酸鉛および二酸化ニオブを成分とする誘電材、又はマ
ンガン・ニオブ酸鉛。
The intermediate layer made of the dielectric material may be a dielectric material containing manganese/lead niobate, magnesium/lead tungstate, lead titanate, and niobium dioxide, or manganese/lead niobate.

ニッケルニオブ酸鉛、マグネシウム・タングステン酸、
チタン酸鉛及びジルコン酸鉛を成分とする誘電材及びマ
ンガン・ニオブ[9、又はマグネシウム酸鉛、ニッケル
・ニオブ酸鉛及びチタン酸鉛を成分とする誘電材を用い
ることができる。
Nickel lead niobate, magnesium tungstic acid,
Dielectric materials containing lead titanate and lead zirconate and manganese-niobium [9], or dielectric materials containing lead magnesium oxide, nickel-lead niobate, and lead titanate can be used.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の断面図、第2図は第1図の
積層構造を示す分解図である。この実施例においてはセ
ラミック多層基板内に構成されるコンデンサは単純な一
対の対向内部電極を有するものについて説明する。
FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is an exploded view showing the laminated structure of FIG. 1. In this embodiment, a capacitor constructed within a ceramic multilayer substrate will be described as having a simple pair of internal electrodes facing each other.

第1図において、本発明のコンデンサ素子内蔵セラミッ
ク多層基板は、誘電材からなる誘電体層21内に、内部
電極3が形成された誘電体層の両件面に絶縁材よりなる
絶縁体層22が積層され、絶縁体層22の各外面に外部
電極13が形成され、内部電極3と外部電極13との間
を誘電体層21、中間層5、および絶縁体層22を通し
て内部配線23により接続する。
In FIG. 1, the ceramic multilayer substrate with a built-in capacitor element of the present invention has a dielectric layer 21 made of a dielectric material, and an insulator layer 22 made of an insulating material on both sides of the dielectric layer 21 on which internal electrodes 3 are formed. are laminated, an external electrode 13 is formed on each outer surface of the insulating layer 22, and an internal wiring 23 connects the internal electrode 3 and the external electrode 13 through the dielectric layer 21, the intermediate layer 5, and the insulating layer 22. do.

第2図により、本発明の積層構造の一実施例について、
詳細に説明する。誘電性セラミックシート(以下誘電シ
ートという)1は、鉄・ニオブ酸鉛、鉄・タングステン
酸鉛、亜鉛・ニオブ酸鉛およびマンガン・ニオブ酸鉛を
成分とする誘電材(以下誘電材DYという)からなる粉
末に有機系のバインダーを加えて混練し、ドクター・ブ
レード法で形成した厚さ約50μmのシートであって、
誘電シート1の所望する位置に上下シートの導通用バイ
アホール2が設けられる。内部電極3は、誘電シート1
の片面に銀・パラジウムを含有する導電ペーストを被着
させて形成される。
FIG. 2 shows an embodiment of the laminated structure of the present invention.
Explain in detail. The dielectric ceramic sheet (hereinafter referred to as dielectric sheet) 1 is made from a dielectric material (hereinafter referred to as dielectric material DY) containing iron/lead niobate, iron/lead tungstate, zinc/lead niobate, and manganese/lead niobate. A sheet with a thickness of about 50 μm formed by adding an organic binder to powder and kneading it and forming it by a doctor blade method,
Via holes 2 for conduction between the upper and lower sheets are provided at desired positions on the dielectric sheet 1. The internal electrode 3 is a dielectric sheet 1
It is formed by depositing a conductive paste containing silver and palladium on one side of the plate.

中間層を構成する誘電シート(以下中間層シートという
)5は、マンガン・ニオブ酸鉛、マグネシウム・タング
ステン酸鉛、チタン酸鉛及び酸化ニオブを成分とする誘
電性セラミック材料(以下誘電材DXという)から、誘
電シート1と同様の方法で作製された誘電シートであり
、バイアホール2が穿設され、4はバイアホール2を囲
んで導電ペーストを被着した円または矩形のランドを示
す。
The dielectric sheet (hereinafter referred to as intermediate layer sheet) 5 constituting the intermediate layer is a dielectric ceramic material (hereinafter referred to as dielectric material DX) containing manganese/lead niobate, magnesium/lead tungstate, lead titanate, and niobium oxide as components. This is a dielectric sheet produced by the same method as dielectric sheet 1, in which a via hole 2 is formed, and 4 indicates a circular or rectangular land surrounding the via hole 2 and covered with a conductive paste.

絶縁性セラミックグリーンシート(以下絶縁シートとい
う)10は誘電シート1の上下に配設するもので、酸化
アルミニウムと硼珪酸鉛系ガラスを主成分とする。11
はそれぞれの絶縁シート10の所定の位置に設けたバイ
アホールである。
Insulating ceramic green sheets (hereinafter referred to as insulating sheets) 10 are disposed above and below the dielectric sheet 1, and are mainly composed of aluminum oxide and lead borosilicate glass. 11
are via holes provided at predetermined positions in each insulating sheet 10.

12は上述の中間層シート5の場合と同様の方法で形成
したランド、13は最外層に導電ペーストを被着して形
成した端子材用外部電極である。上述の絶縁シート10
.誘電シート1および中間層シート5を熱圧着して、未
焼成コンデンサ素子内蔵セラミック多層基板を形成する
。この未焼成コンデンサ素子内蔵セラミック多層基板を
800〜900℃で焼成することによってコンデンサ素
子内蔵セラミック多層基板が形成される。ここで、積層
された誘電シート1は誘電体層21(第1図)に、絶縁
シート10は絶縁体層22(第1図)に、中間層シート
5は中間層24(第1図)に、それぞれ焼成により、形
成される。
12 is a land formed in the same manner as in the case of the above-mentioned intermediate layer sheet 5, and 13 is an external electrode for a terminal material formed by applying a conductive paste to the outermost layer. The above-mentioned insulation sheet 10
.. The dielectric sheet 1 and the intermediate layer sheet 5 are thermocompression bonded to form a ceramic multilayer substrate with a built-in green capacitor element. By firing this unfired ceramic multilayer substrate with a built-in capacitor element at 800 to 900° C., a ceramic multilayer substrate with a built-in capacitor element is formed. Here, the laminated dielectric sheet 1 is placed on the dielectric layer 21 (Fig. 1), the insulating sheet 10 is placed on the insulating layer 22 (Fig. 1), and the intermediate layer sheet 5 is placed on the intermediate layer 24 (Fig. 1). , are formed by firing, respectively.

前述したように従来のコンデンサ素子内蔵セラミック多
層基板では、絶縁体層22中の絶縁材は、誘電体層21
との相互拡散により誘電材と反応する。その結果、誘電
材が変質して比誘電率の低い材料となり、また焼結性も
低下するので、本来誘電性セラミックが発現すべきコン
デンサ容量を著しく低下させてしまう。また、誘電材と
絶縁材との熱収縮特性が異なるために機械的強度に劣る
誘電体層21内にマイクロクラック、誘電体層21と絶
縁体層22との間に眉間剥離が生じ、誘電体層21のコ
ンデンサ容量と耐湿負荷特性の低下が引き起こされる。
As mentioned above, in the conventional ceramic multilayer substrate with a built-in capacitor element, the insulating material in the insulating layer 22 is different from the dielectric layer 21.
Reacts with the dielectric material by interdiffusion with the dielectric material. As a result, the dielectric material changes in quality and becomes a material with a low dielectric constant, and the sinterability also decreases, resulting in a significant reduction in the capacitance that should originally be exhibited by the dielectric ceramic. In addition, microcracks occur in the dielectric layer 21, which has poor mechanical strength due to the difference in heat shrinkage characteristics between the dielectric material and the insulating material, and peeling occurs between the dielectric layer 21 and the insulating layer 22, resulting in This causes a decrease in the capacitor capacity and moisture load resistance of layer 21.

しかし、本発明における中間層24は、成分である誘電
材DXが誘電材DYと比べて絶縁材との反応性が低く、
絶縁材と誘電材DYの拡散を著しく減少させ、かつ第3
図に示したように、中間層の成分である誘電材DXの熱
収縮特性が絶縁材の熱収縮特性と誘電材DYの熱収縮特
性との間にあるために、絶縁体層と誘電体層間の熱収縮
特性の違いによって生じる熱応力を大きく緩和する働き
があり、従って第5図の中間層のない従来の構造では、
内蔵コンデンサの比誘電率が約1500であるのに対し
、第1図の本発明の中間層24を設けた構造では、誘電
材の変質が減少し、また焼結性も向上するために、比誘
電率は約6000と約4倍に向上する。
However, in the intermediate layer 24 in the present invention, the component dielectric material DX has lower reactivity with the insulating material than the dielectric material DY.
Significantly reduces the diffusion of insulating and dielectric materials DY, and
As shown in the figure, the heat shrinkage characteristics of the dielectric material DX, which is a component of the intermediate layer, are between those of the insulating material and that of the dielectric material DY. Therefore, in the conventional structure without an intermediate layer as shown in Fig. 5,
While the built-in capacitor has a specific dielectric constant of about 1500, the structure with the intermediate layer 24 of the present invention shown in FIG. The dielectric constant is approximately 6000, which is approximately four times higher.

第4図は本発明の他の実施例の断面図である。FIG. 4 is a sectional view of another embodiment of the invention.

この実施例においては、セラミック多層基板内に精成さ
れるコンデンサは単純な一対の対向電極を有するものに
ついて説明する。
In this embodiment, a capacitor formed in a ceramic multilayer substrate has a simple pair of opposing electrodes.

第4図において、本発明のコンデンサ素子内蔵セラミッ
ク多層基板は、誘電材DXよりなる中間層24内に内部
電極3が形成される。内部電極3が形成された中間層の
各内面に誘電材DYよりなる誘電体層22が形成される
。内部電極3が形成された中間層24の各外側にそれぞ
れ絶縁材からなる絶縁体層22が積層され、絶縁体層2
2の各外面に外部電極13が形成され、内部電極3と外
部電極13との間を中間M24および絶縁体層22を通
して内部配線23より接続する。上記第2の実施例にお
いて誘電シート、中間層シート。
In FIG. 4, in the ceramic multilayer substrate with a built-in capacitor element of the present invention, internal electrodes 3 are formed in an intermediate layer 24 made of a dielectric material DX. A dielectric layer 22 made of a dielectric material DY is formed on each inner surface of the intermediate layer on which the internal electrodes 3 are formed. An insulator layer 22 made of an insulating material is laminated on each outer side of the intermediate layer 24 on which the internal electrode 3 is formed, and the insulator layer 2
An external electrode 13 is formed on each outer surface of the internal electrode 2, and an internal wiring 23 connects the internal electrode 3 and the external electrode 13 through the intermediate M24 and the insulating layer 22. In the second embodiment above, the dielectric sheet and the intermediate layer sheet.

絶縁シート、電極に用いる材料は第1の実施例と全て同
じである。内部電極は中間層シート5に第1の実施例の
誘電シート1に施した方法と同一の方法で形成される。
The materials used for the insulating sheet and electrodes are all the same as in the first embodiment. The internal electrodes are formed on the intermediate layer sheet 5 by the same method as that applied to the dielectric sheet 1 of the first embodiment.

誘電シート1におけるバイアホール2とランド4が形成
される。絶縁シート10におけるバイアホール4.ラン
ド2及び外部電極13の形成方法は第1の実施例と同じ
である。
Via holes 2 and lands 4 in dielectric sheet 1 are formed. Via hole in insulating sheet 10 4. The method of forming the land 2 and the external electrode 13 is the same as in the first embodiment.

上述の絶縁シート10.中間層シート5および誘電シー
ト1を熱圧着して未焼成コンデンサ素子内蔵セラミック
多層基板を800〜900℃で焼成することによってコ
ンデンサ素子内蔵セラミック多層基板が形成される0本
実施例においては、中間層(比誘電率;約2000)か
らもコンデンサ容量を得ることができ、中間層と誘電体
層との比誘電率の違いからコンデンサ容量にバリエーシ
ョンを持たせることができる利点がある。
The above-mentioned insulating sheet 10. A ceramic multilayer substrate with a built-in capacitor element is formed by thermocompression bonding the intermediate layer sheet 5 and the dielectric sheet 1 and firing the unfired ceramic multilayer substrate with a built-in capacitor element at 800 to 900°C. The capacitor capacitance can also be obtained from the dielectric constant (relative permittivity: about 2000), and there is an advantage that the capacitor capacitance can be varied based on the difference in relative permittivity between the intermediate layer and the dielectric layer.

なお、上述した第1および第2の実施例では中間層とし
てマンガン・ニオブ酸鉛、マグネシウム・タングステン
酸鉛、チタン酸鉛および酸化ニオブを成分とする誘電材
を用いたが、マンガン・ニオブ酸鉛、ニッケル・ニオブ
酸鉛、マグネシウム・タングステン酸鉛およびチタン酸
鉛を成分とする誘電材、又はマンガン・ニオブ酸鉛、マ
グネシウム・タングステン酸鉛、チタン酸鉛およびジル
コン酸鉛を成分とする誘電材、又は、マンガン・ニオブ
酸鉛、マグネシウム・ニオブ酸鉛、ニッケル・ニオブ酸
鉛およびチタン酸鉛を成分とする誘電材も同様に用いる
ことができる。
In the first and second embodiments described above, dielectric materials containing manganese/lead niobate, magnesium/lead tungstate, lead titanate, and niobium oxide were used as the intermediate layer, but manganese/lead niobate , a dielectric material containing nickel/lead niobate, magnesium/lead tungstate and lead titanate, or a dielectric material containing manganese/lead niobate, magnesium/lead tungstate, lead titanate and lead zirconate, Alternatively, dielectric materials containing manganese/lead niobate, magnesium/lead niobate, nickel/lead niobate, and lead titanate can be similarly used.

〔発明の詳細な 説明したように本発明は、誘電材との反応性が低く熱収
縮特性が誘電材と絶縁材との間にある誘電材からなる誘
電体を中間層として誘電材と絶縁材との間に積層するこ
とにより、誘電材と絶縁材とで生じる拡散の遮蔽、及び
両者の熱収縮特性の違いに起因する誘電材と絶縁材との
界面で発生する応力の緩和が行われ、誘電材の本来有し
ていう高い比誘電率をセラミック多層基板内のコンデン
サ素子に発現させる効果がある。また、中間層に内部電
極を形成することで、中間層と誘電体層の比誘電率の違
いによりコンデンサ容量にバリエーションを持たせられ
る効果がある。
[As described in the detailed description of the invention, the present invention uses a dielectric material made of a dielectric material that has low reactivity with the dielectric material and has heat shrinkage characteristics between those of the dielectric material and the insulating material as an intermediate layer, and a dielectric material and an insulating material. By layering between the dielectric material and the insulating material, the diffusion that occurs between the dielectric material and the insulating material is shielded, and the stress that occurs at the interface between the dielectric material and the insulating material due to the difference in thermal shrinkage characteristics between the two materials is alleviated. This has the effect of allowing the capacitor element within the ceramic multilayer substrate to exhibit the high dielectric constant inherent to the dielectric material. Furthermore, by forming internal electrodes in the intermediate layer, there is an effect that the capacitor capacitance can be varied due to the difference in dielectric constant between the intermediate layer and the dielectric layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図、第2図は第1図に
示す一実施例の分解斜視図、第3図は誘電材(DX)、
誘電材(DY)、絶縁材の熱収縮特性を示す図、第4図
は他の実施例の断面図、第5図は従来のコンデンサ素子
内蔵セラミック多層基板の断面図である。 1・・・誘電シート、2,11・・・バイアホール、3
・・・内部電極、4.12・・・ランド、5・・・中間
層シート、10・・・絶縁シート、13・・・外部電極
、21・・・誘電体層、22・・・絶縁体層、23・・
・内部配線、24・・・中間層、31・・・絶縁材の収
縮率曲線、32・・・誘電材DXの収縮率曲線、33・
・・誘電材DYの収縮率曲線。
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is an exploded perspective view of the embodiment shown in FIG. 1, and FIG. 3 is a dielectric material (DX),
FIG. 4 is a cross-sectional view of another embodiment, and FIG. 5 is a cross-sectional view of a conventional ceramic multilayer substrate with a built-in capacitor element. 1... Dielectric sheet, 2, 11... Via hole, 3
...Internal electrode, 4.12... Land, 5... Intermediate layer sheet, 10... Insulating sheet, 13... External electrode, 21... Dielectric layer, 22... Insulator Layer, 23...
- Internal wiring, 24... Intermediate layer, 31... Shrinkage rate curve of insulating material, 32... Shrinkage rate curve of dielectric material DX, 33.
...Shrinkage rate curve of dielectric material DY.

Claims (1)

【特許請求の範囲】[Claims]  導体パターンが形成された複数の絶縁体層の間に、導
体パターンが形成された誘電体層が挟持されたコンデン
サ素子内蔵セラミック多層基板において、前記絶縁体層
と前記誘電体層との間に、絶縁体層と反応性が低く熱収
縮特性が誘電体層と絶縁体層との間にあり、かつ前記誘
電体層とは組成が異なる誘電材料からなる中間層が挟持
されることを特徴とするコンデンサ素子内蔵セラミック
多層基板。
In a ceramic multilayer substrate with a built-in capacitor element in which a dielectric layer on which a conductor pattern is formed is sandwiched between a plurality of insulator layers on which a conductor pattern is formed, between the insulator layer and the dielectric layer, An intermediate layer is sandwiched between the dielectric layer and the insulating layer, which is made of a dielectric material that has low reactivity with the insulating layer, has a heat shrinkage property, and has a composition different from that of the dielectric layer. Ceramic multilayer board with built-in capacitor element.
JP63092065A 1988-04-13 1988-04-13 Ceramic multilayer board having built-in capacitor Pending JPH01262695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63092065A JPH01262695A (en) 1988-04-13 1988-04-13 Ceramic multilayer board having built-in capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63092065A JPH01262695A (en) 1988-04-13 1988-04-13 Ceramic multilayer board having built-in capacitor

Publications (1)

Publication Number Publication Date
JPH01262695A true JPH01262695A (en) 1989-10-19

Family

ID=14044072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63092065A Pending JPH01262695A (en) 1988-04-13 1988-04-13 Ceramic multilayer board having built-in capacitor

Country Status (1)

Country Link
JP (1) JPH01262695A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03285395A (en) * 1990-03-31 1991-12-16 Fujitsu Ltd Manufacture of multilayer glass/ceramic circuit board
EP1320286A3 (en) * 2001-12-13 2005-01-05 Harris Corporation Electronic module including a low temperature co-fired ceramic (LTCC) substrate with a capacitive structure embedded therein and related methods
WO2024070529A1 (en) * 2022-09-26 2024-04-04 株式会社村田製作所 Capacitor element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03285395A (en) * 1990-03-31 1991-12-16 Fujitsu Ltd Manufacture of multilayer glass/ceramic circuit board
EP1320286A3 (en) * 2001-12-13 2005-01-05 Harris Corporation Electronic module including a low temperature co-fired ceramic (LTCC) substrate with a capacitive structure embedded therein and related methods
US7141129B2 (en) * 2001-12-13 2006-11-28 Harris Corporation Electronic module including a low temperature co-fired ceramic (LTCC) substrate with a capacitive structure embedded therein and related methods
WO2024070529A1 (en) * 2022-09-26 2024-04-04 株式会社村田製作所 Capacitor element

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