JPH1126291A - Chip capacitor array - Google Patents

Chip capacitor array

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Publication number
JPH1126291A
JPH1126291A JP17616097A JP17616097A JPH1126291A JP H1126291 A JPH1126291 A JP H1126291A JP 17616097 A JP17616097 A JP 17616097A JP 17616097 A JP17616097 A JP 17616097A JP H1126291 A JPH1126291 A JP H1126291A
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Japan
Prior art keywords
capacitor array
internal electrodes
electrodes
formed
internal
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Pending
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JP17616097A
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Japanese (ja)
Inventor
Kazuyuki Tanaka
一幸 田中
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Taiyo Yuden Co Ltd
太陽誘電株式会社
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Priority to JP17616097A priority Critical patent/JPH1126291A/en
Publication of JPH1126291A publication Critical patent/JPH1126291A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/38Multiple capacitors, i.e. structural combinations of fixed capacitors

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor array with which the generation of crosstalks can be reduced. SOLUTION: Multiple inner electrodes 22, each having a specified area, are placed with specified spaces to form an inner electrode layer. An approximately rectangular parallelepiped element is formed by alternately layering inner electrode layers and dielectric layers 21a and 21b. Multiple pairs of outer electrode which connect in parallel for conduction each row of the inner electrodes 22 formed in the inner electrode layers alternately in the direction of lamination at both ends of the element are formed to constitute a chip capacitor array 20. In this case, the inner electrode 22 are formed in such a manner that the sides of the inner electrodes 22 opposite the sides of adjacent inner electrodes in the same inner electrode layer are curved toward the inside of the inner electrodes 22. As a result, floating capacity produced between inner electrodes 22 is reduced and crosstalks between signals due to the floating capacity are reduced.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、クロストークの低減を図ったチップ型コンデンサアレイに関するものである。 BACKGROUND OF THE INVENTION The present invention relates to a chip type capacitor array thereby reducing the crosstalk.

【0002】 [0002]

【従来の技術】近年、電子回路の小型化及び集積化が進み、これに伴い個々の電子部品の複合化やアレイ化が行われている。 In recent years, miniaturization and integration of electronic circuits progresses, this with complexed or array of individual electronic components have been made. この様なアレイ電子部品の一例として、図2乃至図4に示すように、複数個のコンデンサを一体化形成したチップ型コンデンサアレイの需要も増大している。 An example of such an array electronic components, as shown in FIGS. 2 to 4, the demand for the chip-type capacitor array integrated forming a plurality of capacitors is also increasing.

【0003】図1は従来例のチップ型コンデンサアレイを示す外観斜視図、図2は要部分解斜視図、図3は平面図、図4は図3のA−A線矢視方向断面図である。 [0003] Figure 1 is an external perspective view showing a chip-type capacitor array of the conventional example, FIG. 2 is a fragmentary partially exploded perspective view, FIG. 3 is a plan view, FIG. 4 is a A-A direction indicated by the arrow cross-sectional view of FIG. 3 is there. 図において、10は積層型のコンデンサアレイで、一の誘電体層11上に複数の内部電極12を並列に形成したものを複数積層してなる素体13と、素体13の両端部において内部電極12を積層方向に交互に並列に接続している複数対の外部電極14とから構成され、内部に独立した4個の積層コンデンサ10a,10b,10c,10 In the figure, inside the laminate type capacitor array, with the element body 13 formed by stacking a plurality of those formed in parallel a plurality of internal electrodes 12 on first dielectric layer 11, at the ends of the element body 13 10 It is constituted of the electrode 12 from the plurality of pairs of external electrodes 14 for connecting in parallel alternately in the lamination direction, the four multilayer capacitors 10a independent inside, 10b, 10c, 10
dが形成されている。 d is formed.

【0004】個々の積層コンデンサ10a〜10dにおいて、内部電極12は、所定面積を有する矩形状をなし、その長手方向一端部が外部電極14に接続されている。 [0004] In each of the multilayer capacitor 10 a to 10 d, the internal electrode 12, a rectangular shape having a predetermined area, the one longitudinal end portion is connected to the external electrodes 14.

【0005】誘電体層11は矩形のシート上のセラミック焼結体からなり、セラミック焼結体は、例えばチタン酸バリウム等を主成分とする誘電体磁器材料から形成されている。 [0005] The dielectric layer 11 is made of ceramic sintered body of the rectangular sheet, the ceramic sintered body is formed from a dielectric ceramic material composed mainly of example, barium titanate.

【0006】内部電極12は金属ペーストを焼結させた金属薄膜からなり、金属ペーストとしては、例えばPd [0006] internal electrode 12 is made of a metal thin film obtained by sintering a metal paste, a metal paste, for example, Pd
やAg−Pdのような貴金属材料を主成分とするものが使用され、金属含有量は主に40重量%〜80重量%が用いられている。 And Ag-Pd is mainly composed of noble metal material such as is used, the metal content is mainly used is 40 wt% to 80 wt%.

【0007】外部電極14も内部電極12と同様の材料により形成され、表面には半田濡れ性をよくするために半田メッキが施されている。 [0007] External electrodes 14 are also formed of the same material as the internal electrodes 12, solder plating is applied in order to improve the solder wettability on the surface.

【0008】これにより、前述したコンデンサアレイ1 [0008] Thus, the capacitor array 1 described above
0を1個用いることにより、4つの独立した積層コンデンサ10a〜10dを使用することができるので、回路の小型化、及び部品実装密度の向上を図ることができる。 0 By using one, it is possible to use four separate multilayer capacitor 10 a to 10 d, it is possible to improve the miniaturization and the component mounting density of the circuit.

【0009】 [0009]

【発明が解決しようとする課題】しかしながら、前述したようなコンデンサアレイ10を用いた場合、個々の積層コンデンサ10a〜10dにはそれぞれ異なる信号が印加されるが、コンデンサアレイ10内で隣り合う内部電極12の間隔が非常に狭いため、それぞれの信号間にクロストーク(混信)を生じることがあった。 However [0007] When using the capacitor array 10 as described above, but different signal each of the individual multilayer capacitor 10a~10d is applied, the internal electrodes adjacent in the capacitor array 10. for distance 12 is very small, there may occur cross talk (interference) between the respective signals.

【0010】本発明の目的は上記の問題点に鑑み、クロストークの発生を低減できるコンデンサアレイを提供することにある。 An object of the present invention is to overcome the above-described problems, is to provide a capacitor array capable of reducing the occurrence of crosstalk.

【0011】 [0011]

【課題を解決するための手段】本発明は上記の目的を達成するために請求項1では、所定面積を有する複数の内部電極が所定間隔をあけて並設された内部電極層と誘電体層とを交互に複数積層してなる略直方体形状の素体と、該素体の両端部において前記内部電極層に形成された各列毎の内部電極を積層方向に交互に並列に導電接続している複数対の外部電極とからなるチップ型コンデンサアレイにおいて、前記内部電極は、少なくとも同一内部電極層内で隣り合う内部電極の側辺に対向する側の側辺が、内部電極内側に湾曲した形状をなすチップ型コンデンサアレイを提案する。 The present invention SUMMARY OF] is in claim 1 in order to achieve the above object, the internal electrode layers and dielectric layers having a plurality of internal electrodes are arranged at a predetermined interval with a predetermined area element body having a substantially rectangular parallelepiped shape formed by alternately stacked the door, and electrically connected in parallel to the alternating internal electrodes in each row formed in the internal electrode layers in both end portions of the plain body in the stacking direction shape in a chip-type capacitor array comprising a plurality of pairs of external electrodes are, the internal electrodes, the side of the side facing the side of the internal electrodes adjacent in at least the same internal electrode layer is curved inward internal electrode It proposes a chip-type capacitor array forming a.

【0012】該チップ型コンデンサアレイによれば、前記内部電極は、少なくとも同一内部電極層内で隣り合う内部電極の側辺に対向する側の側辺が、内部電極内側に湾曲した形状をなしているため、内部電極面積の減少を必要最小限に留め、同一内部電極層内で隣り合う内部電極の側辺間の距離を増加させることができるので、該内部電極間に生ずる浮遊容量が低減される。 According to the chip-type capacitor array, wherein the inner electrode is the side of the opposing sides to the sides of the internal electrodes adjacent in at least the same internal electrode layer is a shape curved inwardly internal electrode are therefore retaining the reduction of the internal electrode area to a minimum, it is possible to increase the distance between the side edges of the internal electrodes adjacent in the same internal electrode layers, the stray capacitance is reduced generated between the internal electrodes that.

【0013】また、請求項2では、請求項1記載のチップ型コンデンサアレイにおいて、前記内部電極の側辺は、積層方向に重なる複数の内部電極間において、互いに重なり合う湾曲形状をなしているチップ型コンデンサアレイを提案する。 [0013] According to claim 2, in the chip type capacitor array of claim 1, wherein the side edges of the internal electrodes, between a plurality of internal electrodes which overlap in the stacking direction, a chip-type that forms a curved shape overlapping each other to propose a capacitor array.

【0014】該チップ型コンデンサアレイによれば、前記内部電極の側辺は、積層方向に重なる複数の内部電極間において、互いに重なり合う湾曲形状をなしているため、異なる内部電極層に形成され且つ隣り合う列に位置する内部電極の局部的な接近が低減されるので、これらの内部電極間に生ずる浮遊容量が低減される。 According to the chip-type capacitor array, the sides of the internal electrodes, between a plurality of internal electrodes which overlap in the lamination direction, since a curved shape that overlap each other, adjacent and are formed on different internal electrode layers since local approach of the internal electrodes is reduced which is located row fit, stray capacitance is reduced which occurs between these internal electrodes.

【0015】 [0015]

【発明の実施の形態】以下、本発明の一実施形態を説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention. 図5は本発明の第1の実施形態のチップ型コンデンサアレイを示す外観斜視図、図6は要部分解斜視図、 Figure 5 is an external perspective view showing a chip-type capacitor array of a first embodiment of the present invention, FIG. 6 is a fragmentary partially exploded perspective view,
図7は要部平面図、図8は図7に示すA−A線矢視方向断面図である。 Figure 7 is a fragmentary plan view, FIG. 8 is an A-A direction indicated by the arrow cross-sectional view shown in FIG. 図において、20は積層タイプのチップ型コンデンサアレイで、誘電体層21a,21b上にその長さ方向に4つの内部電極22を並列に形成したもの、及び内部電極を形成しない誘電体層21cを複数積層してなる素体23と、素体23の幅方向両端部において内部電極22を積層方向に交互に並列に接続している4対の外部電極24a〜24hとから構成され、積層方向に列をなした4つの内部電極群によって、素体23内部に独立した4個の積層コンデンサ20a,20b,2 In the figure, 20 is a laminated type chip capacitor array, the dielectric layer 21a, that form four internal electrodes 22 in the longitudinal direction on a parallel 21b, and a dielectric layer 21c which do not form internal electrodes a body 23 formed by stacking a plurality of, consists internal electrode 22 and external electrode 24a~24h four pairs connected in parallel alternately in the lamination direction in the width direction both end portions of the element body 23, in the stacking direction by four internal electrode group in a row, four multilayer capacitors 20a independent inside element 23, 20b, 2
0c,20dが形成されている。 0c, 20d are formed.

【0016】個々の積層コンデンサ20a〜20dにおいて、内部電極22は、その側辺が内部電極22の内側に湾曲した形状をなし、内部電極22の長手方向一端部は、1層毎に対向する外部電極24a〜24hの異なる側に交互に導電接続されている。 [0016] In each of the multilayer capacitor 20a to 20d, the internal electrodes 22, external its sides is a shape curved to the inside of the inner electrode 22, one longitudinal end portion of the inner electrode 22 is opposed to each first layer It is conductively connected alternately to different sides of the electrodes 24a through 24h.

【0017】誘電体層21a〜21cは矩形のシート上のセラミック焼結体からなり、セラミック焼結体は、例えばチタン酸バリウム等を主成分とする誘電体磁器材料から形成されている。 The dielectric layer 21a~21c is a ceramic sintered body on a rectangular sheet, the ceramic sintered body is formed from a dielectric ceramic material composed mainly of example, barium titanate.

【0018】内部電極22は金属ペーストを焼結させた金属薄膜からなり、金属ペーストとしては、例えばPd The internal electrode 22 is made of a metal thin film obtained by sintering a metal paste, a metal paste, for example, Pd
やAg−Pdのような貴金属材料を主成分とするものが使用され、金属含有量は主に40重量%〜80重量%が用いられている。 And Ag-Pd is mainly composed of noble metal material such as is used, the metal content is mainly used is 40 wt% to 80 wt%.

【0019】外部電極24a〜24hも内部電極22と同様の材料により形成され、表面には半田濡れ性をよくするために半田メッキが施されている。 The external electrodes 24a~24h also formed of the same material as the internal electrodes 22, solder plating is applied in order to improve the solder wettability on the surface.

【0020】前述のチップ型コンデンサアレイは次のようにして製造した。 [0020] The foregoing chip capacitor array was prepared as follows. まず、誘電体の原料粉末に有機バインダーを15重量%添加し、さらに水を50重量%加え、これらをボールミルに入れて十分に混合し、誘電体磁器原料のスラリーを作成した。 First, by adding an organic binder 15 wt% to the raw material powder of the dielectric, further adding water 50 wt%, it was thoroughly mixed in a ball mill to prepare a slurry of the dielectric ceramic material.

【0021】次に、このスラリーを真空脱泡器に入れて脱泡した後、リバースロールコーターに入れ、ポリエステルフィルム上にこのスラリーからなる薄膜を形成し、 Next, after defoaming put this slurry to a vacuum degassing vessel, placed in a reverse roll coater, to form a thin film made of the slurry on a polyester film,
この薄膜をポリエステルフィルム上で100℃に加熱して乾燥させ、これを打ち抜いて、10cm角、厚さ約2 The thin film was dried by heating to 100 ° C. on a polyester film, punched them, 10 cm square, a thickness of about 2
0μmのグリーンシートを得た。 To obtain a green sheet of 0μm.

【0022】一方、平均粒径が1.5μmのパラジウム粉末10gと、エチルセルロース0.9gをブチルカルビトール9.1gに溶解させたものとを攪拌器に入れ、 On the other hand, the average particle diameter is 1.5μm palladium powder 10 g, placed in a stirrer and a obtained by dissolving the ethylcellulose 0.9g of butyl carbitol 9.1 g,
10時間攪拌することにより内部電極22用の導電性ペーストを得た。 To obtain a conductive paste for internal electrodes 22 by stirring for 10 hours.

【0023】この後、上述した内部電極22のパターンを200個有する各スクリーンを用いて、上記グリーンシートの片面にこの導電性ペーストからなる内部電極のパターンを各々印刷し、これを乾燥させた。 [0023] Thereafter, with each screen having 200 patterns of the internal electrodes 22 described above, and printing each pattern of internal electrodes consisting of the conductive paste on one surface of the green sheet was dried.

【0024】次に、上記印刷面を上にしてグリーンシートを複数枚積層し、さらにこの積層物の上下両面に印刷の施されていないグリーンシートを積層した。 Next, a green sheet laminating a plurality in the above the printing surface, and further laminating a green sheet which was not subjected to printing on the upper and lower surfaces of the laminate. 次いで、 Then,
この積層物を約50℃の温度で厚さ方向に約40トンの圧力を加えて圧着させた。 The laminate was allowed to crimping by applying a pressure of about 40 tons thickness direction at a temperature of about 50 ° C.. この後、この積層物をカッターにより格子状に裁断し、約50個の積層アレイチップを得た。 Thereafter, by cutting the laminate in a lattice shape by a cutter to obtain about 50 stacked array chip.

【0025】次に、この積層アレイチップを雰囲気焼成可能な炉に入れ、大気中で600℃まで加熱して、有機バインダーを焼成させ、その後、炉の雰囲気を大気中雰囲気とし、積層アレイチップの加熱温度を600℃から焼成温度の1150℃(最高温度)を3時間保持した。 Next, put the stack array chip atmosphere sinterable furnace and heated to 600 ° C. in air, burned organic binder, then, the atmosphere in the furnace and in an air atmosphere, the laminated array chips 1150 ° C. firing temperature and the heating temperature from 600 ° C. to (maximum temperature) and held for 3 hours.
この後、100℃/hrの速度で600℃まで降温し、 Thereafter, the temperature was lowered to 600 ° C. at a rate of 100 ° C. / hr,
室温まで冷却して、焼結アレイチップを得た。 Upon cooling to room temperature to obtain a sintered array chip.

【0026】次いで、焼結アレイチップの端面において内部電極が露出する部分に銀とガラスフリットとビヒクルからなる導電性ペーストを塗布して乾燥させ、これを大気中で800℃の温度で15分間焼き付け、銀電極層を形成し、さらにこの上に銅を無電解メッキで被着させ、この上に電気メッキ法でPb−Sn半田層を設けて、複数対の外部電極24a〜24hを形成した。 [0026] Then, dried by applying a conductive paste made of silver and glass frit and vehicle portion where the internal electrodes exposed at the end surface of the sintered array chip, which baked 15 minutes at a temperature of 800 ° C. in air , to form a silver electrode layer, further the upper is deposited by electroless plating of copper, this on the provided Pb-Sn solder layer by electroplating method to form the external electrodes 24a~24h pairs. これによってチップ型コンデンサアレイ20が得られた。 This chip-type capacitor array 20 is obtained.

【0027】前述の構成よりなるチップ型コンデンサアレイ20によれば、1個のコンデンサアレイ20を用いることにより、4つの独立した積層コンデンサ20a〜 According to the chip-type capacitor array 20 has the constitution described above, by using a single capacitor array 20, four separate multilayer capacitor 20a~
20dを使用することができるので、回路の小型化、及び部品実装密度の向上を図ることができる。 It is possible to use 20d, it is possible to improve miniaturization, and the component mounting density of the circuit.

【0028】また、内部電極22は、同一内部電極層内で隣り合う内部電極22の側辺に対向する側の側辺が、 Further, the internal electrode 22, the side of the side facing the side of the internal electrode 22 adjacent in the same internal electrode layer is,
内部電極22の内側に湾曲した形状をなしているため、 Since has a shape which is curved inwardly of the inner electrode 22,
内部電極22の面積の減少を必要最小限に留めて静電容量を確保し、且つ同一内部電極層内で隣り合う内部電極22の側辺間の距離を増加させることができるので、同一層内で隣り合う内部電極22間に生ずる浮遊容量が低減される。 Securing the capacitance bear to a minimum the reduction of the area of ​​the internal electrode 22, so and it is possible to increase the distance between the side edges of the internal electrodes 22 adjacent in the same internal electrode layer, the same layer stray capacitance generated between the internal electrodes 22 adjacent in is reduced. これにより、この浮遊容量によって生じる異なる信号間のクロストークが低減される。 Thus, crosstalk between different signals generated by the stray capacitance is reduced.

【0029】次に、本発明の第2の実施形態を図9乃至図11に基づいて説明する。 Next, a second embodiment of the present invention will be described with reference to FIGS. 9 to 11. 図9は本発明の第2の実施形態のチップ型コンデンサアレイ30を示す要部分解斜視図、図10のは要部平面図、図11は図10に示すA Figure 9 is a second embodiment principal portion exploded perspective view showing a chip-type capacitor array 30 of FIG. 10 is given fragmentary plan view of the present invention, FIG. 11 A shown in FIG. 10
−A線矢視方向断面図である。 Is -A direction indicated by the arrow cross-sectional view. 図において、前述した第1の実施形態と同一構成部分は同一符号をもって表しその説明を省略する。 In the figure, the same components as those of the first embodiment described above is omitted the same symbols are. また、第1の実施形態と第2の実施形態との相違点は、内部電極の形状を変えたことにある。 Moreover, differences between the first embodiment and the second embodiment is that by changing the shape of the internal electrodes.

【0030】即ち、第2の実施形態における内部電極2 [0030] That is, the internal electrode 2 of the second embodiment
5は、積層方向に重なる複数の内部電極間において、内部電極25の側辺が互いに重なり合う湾曲形状となるように形成されている。 5, between a plurality of internal electrodes which overlap in the stacking direction, the side of the internal electrode 25 is formed so as to overlap the curved shape.

【0031】これにより、異なる内部電極層に形成され且つ隣り合う列に位置する内部電極25が局部的に接近することがないので、これらの内部電極間に生ずる浮遊容量が低減され、第1の実施形態の構成に比べて、さらに浮遊容量の低減を図ることができる。 [0031] Thus, different because the internal electrode 25 located inside electrode layer is formed and adjacent rows will not be locally close, stray capacitance generated between these internal electrodes is reduced, the first compared to the configuration in the embodiment, it is possible to further reduce the stray capacitance.

【0032】即ち、第1の実施形態では、同一内部電極層内では隣り合う内部電極22間の距離を増すことができるが、異なる層に配置された内部電極22を見ると、 [0032] That is, in the first embodiment, it is possible to increase the distance between adjacent internal electrodes 22 in the same internal electrode layer, looking at the internal electrodes 22 disposed in different layers,
例えば図12の(a)(b)に示すような局部的に接近する部分Pが複数存在する。 For example locally accessible to part P as shown in (a) (b) of FIG. 12 there are a plurality.

【0033】これに対し、第2の実施形態の構成においては、異なる層に配置された内部電極25を見ても、図13の(a)(b)に示すように、局部的に接近する部分Pは必要最小限の数となる。 [0033] In contrast, in the configuration of the second embodiment, even look inside electrode 25 disposed in different layers, as shown in (a) (b) of FIG. 13, locally close part P is the number of required minimum.

【0034】ここで、図12の(b)は図12の(a) [0034] Here, in FIG. 12 (b) shown in FIG. 12 (a)
に示すA−A線矢視方向断面図であり、図13の(b) An A-A direction indicated by the arrow cross-sectional view shown in, shown in FIG. 13 (b)
は図13の(a)に示すA−A線矢視方向断面図である。 It is an A-A direction indicated by the arrow cross-sectional view shown in FIG. 13 (a).

【0035】従って、第2の実施形態のチップ型コンデンサアレイ30の構成によれば、異なる内部電極層に形成され且つ隣り合う列に位置する内部電極25が局部的に接近することがないため、これらの内部電極間に生ずる浮遊容量が低減されるので、該浮遊容量によって生じるクロストークをさらに減らすことができる。 [0035] Therefore, according to the configuration of the chip-type capacitor array 30 of the second embodiment, since the internal electrode 25 located adjacent rows and are formed on different internal electrode layers is not able to locally approach, since the stray capacitance generated between these internal electrodes is reduced, it is possible to further reduce crosstalk caused by the stray capacitance.

【0036】尚、前述した第1及び第2の実施形態におけるチップ型コンデンサアレイの構成は一例であり、本願発明がこれらに限定されることはない。 [0036] Incidentally, the configuration of a chip-type capacitor array in the first and second embodiments described above is an example and does not present invention is not limited thereto. 例えば、前述した第1及び第2の実施形態では、両端部に配置された積層コンデンサ20a,20dの内部電極22,26も他のコンデンサの内部電極22,26と同様の形状としたが、本発明では、同一内部電極層内で隣り合う内部電極22,25の側辺に対向する側の側辺が、内部電極2 For example, in the first and second embodiments described above, the multilayer capacitor 20a arranged at both ends, but the internal electrode 22, 26 of 20d was also the same shape as the internal electrodes 22, 26 of other capacitors, the the invention, the side of the side facing the side of the internal electrodes 22 and 25 adjacent in the same internal electrode layer is, the internal electrode 2
2,25の内側に湾曲した形状をなしていれば、前述した効果を奏するものであるので、図14及び図15に示すチップ型コンデンサアレイ20',30'のように、 If a curved shape inwardly of 2.25, so in which the effect described above, the chip type capacitor array 20 shown in FIGS. 14 and 15 ', 30' as,
両端部に配置された積層コンデンサ20a,20dは、 Multilayer capacitor 20a arranged at both ends, 20d are
その内部電極22,26として、隣り合うコンデンサが存在しない側の側辺を湾曲させずに直線状に形成した内部電極22',25'を用いても良い。 As its internal electrode 22, 26, the internal electrode 22 was formed in a linear shape without bending the lateral sides there are no adjacent capacitors ', 25' may be used.

【0037】 [0037]

【発明の効果】以上説明したように本発明の請求項1記載のチップ型コンデンサアレイによれば、内部電極の側辺が湾曲した形状をなし、内部電極面積の減少を必要最小限に留めた状態で、同一内部電極層内で隣り合う内部電極の側辺間の距離が増加するため、該内部電極間に生ずる浮遊容量が低減されるので、該浮遊容量によって生じる異なる信号間のクロストークが低減される。 According to the chip-type capacitor array of claim 1 wherein the the present invention as described in the foregoing, a shape that the side of the internal electrode is bent and fastened to a minimum the reduction of the internal electrode area state, the distance between the sides of the internal electrodes adjacent in the same internal electrode layer is increased, since the stray capacitance generated between the internal electrodes is reduced, crosstalk between different signal caused by the stray capacitance It is reduced.

【0038】また、請求項2記載のチップ型コンデンサアレイによれば、上記の効果に加えて、異なる内部電極層に形成され且つ隣り合う列に位置する内部電極の局部的な接近が低減されるため、これらの内部電極間に生ずる浮遊容量がさらに減少し、該浮遊容量によって生じるクロストークをさらに低減することができる。 Further, according to the chip capacitor array according to claim 2, wherein, in addition to the above effects, local proximity of the internal electrode located adjacent rows and are formed on different internal electrode layers is reduced Therefore, it is possible to stray capacitance generated between these internal electrodes is further reduced to further reduce crosstalk caused by the stray capacitance.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】従来例のコンデンサアレイを示す外観斜視図 Figure 1 is an external perspective view showing a capacitor array of the prior art

【図2】従来例のコンデンサアレイを示す要部分解斜視図 [2] main portion exploded perspective view showing a capacitor array of the prior art

【図3】従来例のコンデンサアレイを示す平面図 Figure 3 is a plan view showing a capacitor array of the prior art

【図4】図3のA−A線矢視方向断面図 [4] A-A direction indicated by the arrow cross-sectional view of FIG. 3

【図5】本発明の第1の実施形態のコンデンサアレイを示す外観斜視図 Figure 5 is an external perspective view showing a capacitor array of the first embodiment of the present invention

【図6】本発明の第1の実施形態のコンデンサアレイを示す要部分解斜視図 [6] main portion exploded perspective view showing a capacitor array of the first embodiment of the present invention

【図7】本発明の第1の実施形態のコンデンサアレイを示す要部平面図 [7] fragmentary plan view showing a capacitor array of the first embodiment of the present invention

【図8】図7に示すA−A線矢視方向断面図 [8] A-A direction indicated by the arrow cross-sectional view shown in FIG. 7

【図9】本発明の第2の実施形態のコンデンサアレイを示す要部分解斜視図 [9] main portion exploded perspective view showing a capacitor array of the second embodiment of the present invention

【図10】本発明の第2の実施形態のコンデンサアレイを示す要部平面図 [10] fragmentary plan view showing a capacitor array of the second embodiment of the present invention

【図11】図10に示すA−A線矢視方向断面図 [11] A-A direction indicated by the arrow cross-sectional view shown in FIG. 10

【図12】本発明の第1の実施形態と第2の実施形態との相違を説明する図 Diagram for explaining the differences between the first embodiment and the second embodiment of the present invention; FIG

【図13】本発明の第1の実施形態と第2の実施形態との相違を説明する図 Diagram for explaining the differences between the first embodiment and the second embodiment of Figure 13 the present invention

【図14】本願発明の他の実施形態の要部構成を説明する図 FIG. 14 illustrates a configuration of a main part of another embodiment of the present invention

【図15】本願発明の他の実施形態の要部構成を説明する図 Figure 15 is a diagram illustrating a configuration of a main part of another embodiment of the present invention

【符号の説明】 DESCRIPTION OF SYMBOLS

20,30…チップ型コンデンサアレイ、20a〜20 20, 30 ... chip-type capacitor array, 20a~20
d…積層コンデンサ、21a〜21c…誘電体層、2 d ... multilayer capacitor, 21a~21c ... dielectric layer, 2
2,22',25,25'…内部電極、23…素体、2 2,22 ', 25, 25' ... inner electrode, 23 ... base body, 2
4a〜24h…外部電極。 4a~24h ... external electrode.

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 所定面積を有する複数の内部電極が所定間隔をあけて並設された内部電極層と誘電体層とを交互に複数積層してなる略直方体形状の素体と、該素体の両端部において前記内部電極層に形成された各列毎の内部電極を積層方向に交互に並列に導電接続している複数対の外部電極とからなるチップ型コンデンサアレイにおいて、 前記内部電極は、少なくとも同一内部電極層内で隣り合う内部電極の側辺に対向する側の側辺が、内部電極内側に湾曲した形状をなすことを特徴とするチップ型コンデンサアレイ。 1. A element body having a substantially rectangular parallelepiped shape formed by laminating a plurality a plurality of internal electrodes and internal electrode layers and dielectric layers are juxtaposed at predetermined intervals alternately with a predetermined area, the plain body in the chip type capacitor array comprising a plurality of pairs of external electrodes are electrically connected to internal electrodes in parallel alternately in the stacking direction of each row formed on the inner electrode layer at both end portions of said internal electrodes, at least the same side of the side facing the side of the internal electrode layers in a neighboring inner electrodes, the chip type capacitor array, characterized in that a shape which is curved inwardly internal electrodes.
  2. 【請求項2】 前記内部電極の側辺は、積層方向に重なる複数の内部電極間において、互いに重なり合う湾曲形状をなしていることを特徴とする請求項1記載のチップ型コンデンサアレイ。 Side of wherein said internal electrodes, between a plurality of internal electrodes which overlap in the stacking direction, the chip-type capacitor array of claim 1, wherein in that a curved shape overlapping each other.
JP17616097A 1997-07-01 1997-07-01 Chip capacitor array Pending JPH1126291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006093531A (en) * 2004-09-27 2006-04-06 Matsushita Electric Ind Co Ltd Dielectric substrate for lamination and multilayer capacitor
US7411776B2 (en) 2006-07-12 2008-08-12 Tdk Corporation Multilayer capacitor array
US7558049B1 (en) 2007-12-20 2009-07-07 Tdk Corporation Multilayer capacitor array
US7948737B2 (en) 2007-12-11 2011-05-24 Tdk Corporation Multilayer capacitor array
CN102269520A (en) * 2011-06-28 2011-12-07 中国原子能科学研究院 Mirror high-temperature furnace device for neutron diffraction sample in-situ experiment
US8107214B2 (en) 2008-02-13 2012-01-31 Tdk Corporation Multilayer capacitor array having terminal conductor, to which internal electrodes are connected in parallel, connected in series to external electrodes
KR101153686B1 (en) * 2010-12-21 2012-06-18 삼성전기주식회사 Fabricating method for multi layer ceramic electronic device and multi layer ceramic electronic device using thereof
US8498096B2 (en) 2010-05-10 2013-07-30 Murata Manufacturing Co., Ltd. Electronic component
US8760847B2 (en) 2010-11-30 2014-06-24 Pratt & Whitney Canada Corp. Low inductance capacitor assembly
US8902563B2 (en) 2012-04-26 2014-12-02 Samsung Electro-Mechancis Co., Ltd. Multilayer ceramic electronic component

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006093531A (en) * 2004-09-27 2006-04-06 Matsushita Electric Ind Co Ltd Dielectric substrate for lamination and multilayer capacitor
JP4569246B2 (en) * 2004-09-27 2010-10-27 パナソニック株式会社 Multilayer capacitors and molded capacitors
US7411776B2 (en) 2006-07-12 2008-08-12 Tdk Corporation Multilayer capacitor array
US7948737B2 (en) 2007-12-11 2011-05-24 Tdk Corporation Multilayer capacitor array
US7558049B1 (en) 2007-12-20 2009-07-07 Tdk Corporation Multilayer capacitor array
US8107214B2 (en) 2008-02-13 2012-01-31 Tdk Corporation Multilayer capacitor array having terminal conductor, to which internal electrodes are connected in parallel, connected in series to external electrodes
US8498096B2 (en) 2010-05-10 2013-07-30 Murata Manufacturing Co., Ltd. Electronic component
US10515763B2 (en) 2010-11-30 2019-12-24 Pratt & Whitney Canada Corp. Method of assembling a capacitor assembly
US9761375B2 (en) 2010-11-30 2017-09-12 Pratt & Whitney Canada Corp. Method of assembling a capacitor assembly
US8760847B2 (en) 2010-11-30 2014-06-24 Pratt & Whitney Canada Corp. Low inductance capacitor assembly
KR101153686B1 (en) * 2010-12-21 2012-06-18 삼성전기주식회사 Fabricating method for multi layer ceramic electronic device and multi layer ceramic electronic device using thereof
CN102269520A (en) * 2011-06-28 2011-12-07 中国原子能科学研究院 Mirror high-temperature furnace device for neutron diffraction sample in-situ experiment
US8902563B2 (en) 2012-04-26 2014-12-02 Samsung Electro-Mechancis Co., Ltd. Multilayer ceramic electronic component
US9196421B2 (en) 2012-04-26 2015-11-24 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component

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