JPS62256493A - 遮蔽ペ−スト - Google Patents

遮蔽ペ−スト

Info

Publication number
JPS62256493A
JPS62256493A JP62049018A JP4901887A JPS62256493A JP S62256493 A JPS62256493 A JP S62256493A JP 62049018 A JP62049018 A JP 62049018A JP 4901887 A JP4901887 A JP 4901887A JP S62256493 A JPS62256493 A JP S62256493A
Authority
JP
Japan
Prior art keywords
paste
gold
alumina
substrate
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62049018A
Other languages
English (en)
Japanese (ja)
Other versions
JPH035076B2 (enExample
Inventor
リチヤード・フランシス・インデイツクス
フランシスコ・ジヤヴイア・ラメラス
マーク・オリヴアー・ナイサ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS62256493A publication Critical patent/JPS62256493A/ja
Publication of JPH035076B2 publication Critical patent/JPH035076B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H10W70/666—Organic materials or pastes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
JP62049018A 1986-04-24 1987-03-05 遮蔽ペ−スト Granted JPS62256493A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US855263 1986-04-24
US06/855,263 US4663186A (en) 1986-04-24 1986-04-24 Screenable paste for use as a barrier layer on a substrate during maskless cladding

Publications (2)

Publication Number Publication Date
JPS62256493A true JPS62256493A (ja) 1987-11-09
JPH035076B2 JPH035076B2 (enExample) 1991-01-24

Family

ID=25320789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62049018A Granted JPS62256493A (ja) 1986-04-24 1987-03-05 遮蔽ペ−スト

Country Status (5)

Country Link
US (1) US4663186A (enExample)
EP (1) EP0242558B1 (enExample)
JP (1) JPS62256493A (enExample)
CA (1) CA1279753C (enExample)
DE (1) DE3751658T2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006501661A (ja) * 2002-10-01 2006-01-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 集積回路を接続するための基板
JP2006120759A (ja) * 2004-10-20 2006-05-11 Sony Corp 配線基板の製造方法および半導体装置の製造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL80039A0 (en) * 1986-09-16 1986-12-31 Saul Sterman Method and system for tinting contact lenses
US5654354A (en) * 1991-11-14 1997-08-05 E. I. Du Pont De Nemours And Company Compositions for diffusion patterning
US5275689A (en) * 1991-11-14 1994-01-04 E. I. Du Pont De Nemours And Company Method and compositions for diffusion patterning
JPH08148787A (ja) * 1994-11-21 1996-06-07 Sumitomo Kinzoku Ceramics:Kk 厚膜ペースト
JP4780844B2 (ja) * 2001-03-05 2011-09-28 Ｏｋｉセミコンダクタ株式会社 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3726002A (en) * 1971-08-27 1973-04-10 Ibm Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate
JPS5938268B2 (ja) * 1974-03-22 1984-09-14 カンザキセイシ カブシキガイシヤ 新規フタリド化合物の製造法
US3957552A (en) * 1975-03-05 1976-05-18 International Business Machines Corporation Method for making multilayer devices using only a single critical masking step
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
FR2451899A1 (fr) * 1979-03-23 1980-10-17 Labo Electronique Physique Composition dielectrique, encre serigraphiable comportant une telle composition, et produits obtenus
US4493856A (en) * 1982-03-18 1985-01-15 International Business Machines Corporation Selective coating of metallurgical features of a dielectric substrate with diverse metals
US4442137A (en) * 1982-03-18 1984-04-10 International Business Machines Corporation Maskless coating of metallurgical features of a dielectric substrate
US4526859A (en) * 1983-12-12 1985-07-02 International Business Machines Corporation Metallization of a ceramic substrate
US4582722A (en) * 1984-10-30 1986-04-15 International Business Machines Corporation Diffusion isolation layer for maskless cladding process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006501661A (ja) * 2002-10-01 2006-01-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 集積回路を接続するための基板
JP2006120759A (ja) * 2004-10-20 2006-05-11 Sony Corp 配線基板の製造方法および半導体装置の製造方法

Also Published As

Publication number Publication date
DE3751658D1 (de) 1996-02-15
US4663186A (en) 1987-05-05
EP0242558A3 (en) 1989-03-29
EP0242558A2 (en) 1987-10-28
JPH035076B2 (enExample) 1991-01-24
DE3751658T2 (de) 1996-07-04
CA1279753C (en) 1991-02-05
EP0242558B1 (en) 1996-01-03

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