JPS62254465A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a perfectly buried channel to be formed by a method wherein control electrodes are provided on the peripheral part of semiconductor region of channel forming region of an SOI-MOSFET through the intermediary of insulating films. CONSTITUTION:An MOSFET T1 is composed of an n<+> source region 102, an n<+> drain region 103, an n channel region 104, a gate electrode 106 in an insulating film 105 formed in a thin film type single crystal region formed on an insulating film 101, a lower control electrode 107 provided in the insulating film 101 and an upper control electrode 108 provided on the peripheral part of insulating film 105. The upper and lower control electrodes 107, 108 can be formed of P type polysilicon or metal slightly impressed with standard negative voltage as a bias voltage. Through these procedures, a perfectly buried channel can be formed even if single crystal region is thin film type so that the movement and noise of elements may be markedly improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an SOI-MO8FIE type semiconductor device having a buried channel formed in a thin-film single crystal region.

Research and development of 3D integrated circuits is progressing not only as a way to overcome the limitations of high density and speed performance in conventional 2D VHSX technology, but also as a way to realize new types of composite devices with various functions. The core technology is SOI (Silicon On In5ulat).
or) technology. However, the thickness of the Si single crystal formed by SOR technology is that of single crystal growth.

Thinner films are required to facilitate processing. As a result, when configuring an active element in a thin film-like single crystal region,
Problems that have not been considered in the past may emerge.

Figure 4 shows a basic SOI-MOSF with surface channel type.
This is a cross-sectional view of an ET, in which a source n+ region 402. n-region 403. P region 4o where a channel is formed
4. A gate electrode 406 provided through an insulating film 405,
MO8FICT"Ql" is configured.

An energy band diagram of the thermal equilibrium state corresponding to the DD' cross section of this MOSFET "Q1" is shown in FIG. 6 (IL). The energy band diagram when a positive voltage is applied to the gate electrode 406 is shown by the solid line in FIG. 6(b). As a result, an inversion layer 40 is formed at the interface between the P region 404 and the insulating film 40g.
7 is formed and becomes a surface channel. In this state, when a positive voltage is applied to the n+ region 403 of the drain relative to the source, the energy level of the P region 404 changes to the dotted line 408.
It is also possible that the entire D and P regions become an inversion layer. This state becomes more pronounced as the film thickness of the thin film-like single crystal region becomes thinner. In general, in an 80I single crystal, crystal defects in the single crystal film may occur in the P region 40, although it depends on the method of crystal growth.
It is largest near the lower interface between P region 404 and insulating film 401, and decreases exponentially toward the upper interface between P region 404 and insulating film 405. Of course, the P region 404 and the insulating film 406
Crystal defects increase again at the upper interface with. Furthermore, when a single crystal region is divided, in addition to the above-mentioned upper and lower interfaces, crystal defects at the left and right side interfaces cannot be ignored. It is known that crystal defects at the interface as described above cause performance deterioration of MO8FICT "Ql". (Reference: [Solid-State Electronics J (N, 5ak
alaetaL, 5olid-8t&te Ele
ctronics vol, 22゜pp, 417-42
1.1979 )) FIG. 6 shows a cross-sectional view of a basic buried channel type 30I-MOSFET, in which a source n
+ area 6o2. Drain n+ region 6o3. n region 6o4 where a channel is formed; With the gate electrode 606 provided through the insulating film 605, MO5FICT''t Q 2 I
t is constructed. This MOSFET “Q2” -IC
The energy band diagram of the thermal equilibrium state corresponding to the cross section is shown in FIG. 7(a). In this state, when a positive voltage is applied to the n-region 603 of the drain with respect to the source, the n-region 604
When the energy level is D as shown by the dotted line 701, an inversion layer is likely to be formed at the lower interface between the n region 604 and the insulating film 601 and a lower surface channel is formed.

The energy band diagram when a positive voltage is applied to the gate electrode 606 of MOSFET "Q2" is shown in FIG. 7(b).
When a positive voltage is applied to 3, the energy level of n region 604 becomes D as shown by dotted line 702, and buried channel region 70
3 and an inversion layer at the upper interface between the n region 604 and the insulating film 605 to form an upper surface channel.

Further, MO5FICT “Q2” O gate electrode 60
FIG. 7(C) shows an energy band diagram when the positive voltage applied to 6 is increased. In this state, the n area 604
An upper surface channel is formed by the inversion layer 704 at the upper interface between the n-region 604 and the insulating film 605, and when a positive voltage is applied to the drain with respect to the source, the inversion layer is formed at the lower interface between the n-region 604 and the insulating film 601. It spreads towards.

As an example, FIG. 6 shows the state of the channel corresponding to FIG. 7(b). When looking at the n-region 604 from the source to the drain, the channel is 607 in FIG. 6 (&).
The channel 608 in FIG. 6(b) is seen in a cross section perpendicular to this.

Therefore, even if it is a buried channel when observed in -dimensional terms, if it is a surface channel when observed in three dimensions, MO8FICT ``Q2'' is similar to that described above for MO5FICT ``Q1''. ” performance deteriorates.

Problems to be Solved by the Invention As mentioned above, in the basic SOI-MOSFET, the film thickness of the thin film-like single crystal region is small, so in the conventional structure, the formed channel is a semiconductor with many crystal defects. - Since it includes an insulating film interface, performance deterioration such as mobility and noise is unavoidable.

In view of this, an object of the present invention is to provide a semiconductor device in which a completely buried channel is formed.

Means for Solving the Problems The present invention forms a source region, a drain region, and a channel forming region in a single crystal semiconductor region formed on a first insulating film, and also forms a gate electrode through a second insulating film. is provided, and a control electrode is provided around the channel forming region via a first insulating film or a second insulating film.

Operation The present invention prevents the formation of an inversion layer at the semiconductor-insulating film interface according to the conductivity type of the control electrode or the polarity of the applied bias, thereby realizing a completely buried channel.

Embodiment FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. FIG. 1 (IL) is a top view, and FIG. 1 (b) is a top view. Cross-sectional view, same figure (c) [t
[1(a) or -Y' sectional view is shown.

In FIG. 1, a thin single crystal region formed on an insulating film 101 includes a source n region 102, a drain n+ region 1o3, an n region 104 where a channel is formed, a gate electrode 106 in an insulating film 105, A lower control electrode 107 is provided within the insulating film 101, and an upper control electrode 108 is provided around the insulating film 106.
MO8FKT°°T1'' is configured.

The upper and lower control electrodes 107 and 108 are P-type po as shown in FIG.
It may be formed of ly-8i, or it may be formed of metal and a slight negative voltage is applied as a bias.

The energy band diagram of the thermal equilibrium state corresponding to the Moum 1 cross section of MO8FIET "T1" is shown in the solid line part of Figure 2 (1), and the energy band diagram of the thermal equilibrium state corresponding to the BB' cross section of MO3FICT "T1" is shown in The energy band diagram of the thermal equilibrium state corresponding to the solid line section in FIG. 2(b) and the c-c' cross section of MOSFET "T1" is shown in FIG. 2(0).

As mentioned above, due to the presence of upper and lower and left and right control electrodes, M
The interface between the n-region 1-04 of the OSFET "T1" and the insulating film 106 and the insulating film 1o1 is bent in the direction D shown in FIG. 2 (IL) and (b), so that the surface D, in which a channel is difficult to form, a buried channel 111 is easily formed.

On the other hand, since the gate electrode 106 is provided only near the junction between the source n-region 102 and the channel-forming n-region 104, it converts the buried channel 111 formed in the n-region 104 into a surface channel. It does not have any impact. Moreover, the gate electrode 106 and the upper control electrode 108
Due to the superposition of the effects of
Since the inversion layer is more difficult to form than in the solid line portion of &), a surface channel is less likely to be formed even if a positive voltage is applied to the gate electrode in the main operating state.

Furthermore, when a positive voltage is applied to the drain with respect to the source, the energy band diagram of the n-region 104 in the MO8FICT"Tlol OA AI cross section is as shown in FIG.
The energy band diagram of the n region 104 in the BB' cross section of MO3FICT "T1" is shown in the dotted line part in FIG. Figure (shown in (1).

The buried channel 111 in FIG.
ET”T11t, is S I T (5taticInd
(transistor).

Furthermore, when shifting to SIT, the ``drain current-drain voltage characteristic'' also shifts to an unsaturated type similar to that of a triode, but if the following equation holds between the n-region 104 and the control electrodes 107 and 108, the tetrode, Shifts to a saturated type similar to the triode type.

(D2+H2 Ashiku L...(1) In addition,
The left and right sides of equation (1) correspond to the case where the n area 104 in FIG. 1 is a rectangular parallelepiped, but the left side holds true in the same way when the left side is the diameter in the case of a cylinder, and the long axis in the case of an elliptical cylinder. Also, if the length of the gate electrode 106 above the n region 104 is K, then (D2+H2)<L+K (2)
If this holds true, an upper control electrode 110 shorter than the channel length of the n-region 104 may be provided on the same plane as the gate electrode 106, as shown in FIG. Similarly to the upper control electrode 110, the electrode 109 may also be made shorter than the channel length.

As described above, according to this embodiment, SOI-MOSFE
By providing a control electrode around the semiconductor region of the channel formation region of T via an insulating film, a complete buried channel can be formed even if the thin film-like single crystal region is thin, and the mobility of the element can be improved. Noise is significantly improved.

FIG. 3 shows a three-dimensional integrated circuit with a three-layer structure constructed by applying the structure shown in FIG. 1(d). A source n region 3o2. is formed on the P substrate 301. Drain n region 3o3° insulating film 304
The gate electrode 305 provided through the MOSFET"T2
A thin single crystal region on the insulating film 304 includes a source male region 306, a drain n+ region 3o7, an n region 308 for channel formation, a gate electrode 310 provided through the insulating film 309, and an upper control region. Electrode 311. Insulating film 30
The electrostatic shielding electrode 312 in 4 is MO8F]ETゞゞT
3”.

A source n region 314 . Channel forming n region 316° drain n region
Area 316. Gate electrode 3 provided via insulating film 317
18. The upper control electrode 319° and the electrostatic shielding electrode 313 in the insulating film 309 constitute the MO8FICT0 agent.

In this way, in the case of a multilayer structure, the lower control electrode may be used as an electrostatic shielding electrode. Rather, it completely prevents electrical interference between the upper and lower active layers, and is also effective as a heat sink for element heat generation.

Effects of the Invention As described above, according to the present invention, an MO! 5FKT can be made into a completely buried channel type.

Furthermore, if a buried channel is realized in complete depletion, S
IT can be realized, and depending on the design of the control electrode, SIT with triode characteristics or SIT with tetrade or pentode characteristics can easily be realized.

[Brief explanation of drawings]

FIG. 1(&) is a plan view showing the structure of a semiconductor device according to the first embodiment of the present invention, FIG. 1(b) is FIG. 1(IL)
0) XX' sectional view, Figure 1 (0) is Y in Figure 1 (a)
-Y' sectional view, FIG. 1(d) is a sectional view showing another example of the semiconductor device of FIG. 1(b), and FIG. 2(&) corresponds to FIG. 1 of the first embodiment. 2(b) is an energy band diagram of the cross section B-B', and FIG. 2(C) is an energy band diagram of the cross-section C-C'. d) is an energy band diagram of the c-c' cross section, FIG. 3 is a cross-sectional view of a semiconductor device with a three-layer structure using the first embodiment, and FIG. 4 is a surface channel type SOI
-MO8FXT (D Cross-sectional view of conventional example, Figure 6 (IL)
is an energy band diagram at thermal equilibrium of the cross section of Moom 1 of the conventional example in Figure 4, Figure 5 (b) is an energy band diagram at the same main operation, and Figure 6 (IL) is another conventional buried channel type SOI. - Front sectional view of MO8FXT, Figure 6 (b) is the same side sectional view, Figure 7 (IL), (b), (0)
is an energy band diagram showing correspondence to the IC-x' cross section of the conventional example in FIG. 6, and FIG. 7(d) is an energy band diagram showing correspondence to the FF' cross section of the conventional example. 101.105...Insulating film, 102,103.
...n+ territory area 104...n area, 10
6... Gate electrode, 107... Lower control electrode, 10B... Upper control electrode, T1...
...MO8FICT0 Agent's name: Patent attorney Toshio Nakao and one other person Figure 1, Ln (C) Figure 2, Figure 2 (!I, Figure 3, Figure 4, Figure 7)

Claims (3)

[Claims] (1) A source region, a drain region, and a channel formation region are formed in a single crystal semiconductor region formed on a first insulating film, and a gate electrode is provided through a second insulating film around the channel formation region. A semiconductor device characterized in that a control electrode is provided through a first insulating film or a second insulating film. (2) The control electrode is composed of an upper control electrode and a lower control electrode, and the upper control electrode is provided corresponding to the upper surface and side surface of the channel, and the lower control electrode is provided corresponding to the lower surface of the channel. A semiconductor device according to claim 1. (3) It is characterized in that it is constructed so that (D^2+H^2)^1^/^2<L holds for the vertical interval D of the control electrodes, the horizontal interval H, and the channel length L of the channel forming region. A semiconductor device according to claim 1.