JP3503094B2 - Insulated gate type static induction transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate static induction transistor, and more particularly to an insulated gate static induction transistor having a large driving capability, a small gate capacitance and excellent reliability, and an integrated circuit thereof.

[0002]

2. Description of the Related Art Conventionally, insulated gate field effect transistors (hereinafter referred to as MOSFETs) have been used in logic circuits and memories, and have been miniaturized and highly integrated. This MOSFET exhibits a saturation-type current-voltage characteristic in which the drain current gradually saturates as the drain voltage increases as the drain voltage increases. Figure 11 is MOS
This is the relationship between the drain current and drain voltage of the FET, and each solid line represents the characteristics due to different gate voltages. In both cases, the drain current increases linearly with increasing drain voltage as long as the drain voltage is low,
Saturates at a certain drain voltage.

On the other hand, static induction transistors (hereinafter SI
(Referred to as T) has an unsaturated type current-voltage characteristic in which the drain current continues to increase as the drain voltage increases.
As shown in FIG. 12, each solid line showing the characteristics of different gate voltages represents that the drain current increases as the drain voltage increases. Since it is the potential barrier on the front surface of the source that controls the drain current,
The drain current changes exponentially not only with the gate voltage but also with the drain voltage (J. Nishizawa
et.al., IEEE Trans.on Electron Devices, vol.ED-22,
no. 4, pp.185-197, 1975). In addition, it has been reported that the drain current increases linearly with the drain voltage in the large current region when there is series resistance on the source side (Y. Mochida et.al., IEEE Trans.on. Electr
on Devices, vol.ED-25, no.7, pp.761-767, 1978).

This static induction transistor has the following features. 1. Due to the unsaturated type current-voltage characteristic, the apparent conversion conductance is large, the output current is large, and the output impedance is low. 2. High input impedance because it operates in reverse bias between the gate and source. 3. Since the gate region can have a high impurity density, the gate resistance can be reduced. 4. Since the channel region has a low impurity density and the gate region can be downsized, the electrode capacitance between the gate and the source and between the gate and drain can be reduced. 5. Since the channel region has a low impurity density, high breakdown voltage can be achieved. 6. The amplification coefficient can be kept constant over an extremely wide operating range, and operation with extremely little distortion can be performed. 7. Since the temperature coefficient in high current operation can be made negative, thermal runaway does not occur. In this way, the static induction transistor has high power, high breakdown voltage,
It has excellent characteristics in various aspects such as large current, low distortion, and high speed operation.

Of course, the static induction transistor may be of the insulated gate type (for example, Japanese Patent No. 1320814).
No., hereinafter referred to as MOSSIT), is being prototyped as an element for high-speed, low-power consumption integrated circuits (T. Nakamura
et.al., IEEE J. of SolidState Circuits, vol.SC-13,
no.5, pp.572-576, 1978; J. Nishizawa et.al., IEEE T
rans.on Electron Devices, vol.ED-37, no.8, pp.1877
-1883, 1990).

Since the MOSSIT has an insulating film inserted between the gate and the source, not only has a larger input impedance than the junction type SIT, but also a gate electrode can be formed in the immediate vicinity of the source, so that series resistance is reduced. Drive capacity can be increased. Ie MOSSIT
Basically has excellent characteristics as an element for a high speed and low power consumption integrated circuit.

The conventional MOSSIT will be briefly described. As shown in FIG. 13, MOSSIT has a p-type semiconductor substrate 111 serving as a channel, a thin gate oxide film 112 provided on its main surface and a polycrystalline silicon layer 113 serving as a gate electrode, and a p-type semiconductor substrate 111. And an n-type source region 114 and a drain region 115 each having a high impurity density. The impurity density of the p-type channel is set so that the channel is almost depleted only by the diffusion potential.

The current-voltage characteristic of this MOSSIT is shown in FIG.
4 shows. FIG. 10A shows the relationship between the drain current and the drain voltage, the horizontal axis is the logarithmic plot of the drain voltage, and the vertical axis is the logarithmic plot of the drain current, and each solid line shows the characteristics for different gate voltages. Further, FIG. 7B shows the relationship between the drain current and the gate voltage, the horizontal axis is the logarithmic plot of the gate voltage, and the vertical axis is the logarithmic plot of the drain current, and each solid line shows the characteristics for different drain voltages.

As described above, in MOSSIT, the drain current changes exponentially with respect to the drain voltage and the gate voltage, and the operating region controlled by the potential barrier formed in front of the source region is I know there is. Further, the drain current in a large current region, that is, a region outside the exponential function characteristic is affected not only by the series resistance and space charge but also by the surface inversion layer and the like.

[0010]

SUMMARY OF THE INVENTION One object of the present invention is that the drain current changes exponentially with both the gate voltage and the drain voltage in a wider operating voltage range, and has a driving ability higher than that of a conventional MOSFET. To provide a sufficiently large insulated gate static induction transistor.

Another object of the present invention is that the drain voltage is not shielded by the surface inversion layer, that is, the potential distribution is determined by the electrons in the inversion layer and the potential barrier on the front surface of the source is applied even if the drain voltage is applied. It is an object of the present invention to provide an insulated gate static induction transistor which has a drive capability sufficiently larger than that of a conventional MOS transistor without being difficult to sag.

[0012]

According to a first aspect of the present invention,
Then, the insulated gate static induction transistor has the first conductivity type.
Of high impurities formed on the main surface of semiconductor substrate
Second-conductivity-type source and drain regions having density
And the source region and the drain on the main surface
A second conductivity type provided between the regions and having a low impurity density.
It contacts the channel region and the bottom of the source region, and
A first conductivity type semiconductor region having a material density,
It touches or overlaps the source region and the other end
A gate insulating film formed so as to extend in the channel region,
A gate electrode formed on the gate insulating film,
However, the depth from the surface in the source region is
It is formed shallower than the depth from the surface in the in region,
The edge of the semiconductor region is located before the edge of the source region.
It is formed so as to project to the drain region. Of the present invention
According to a second aspect, an insulated gate electrostatic induction transistor.
The titanium has a main surface and has a low impurity density.
A first conductivity type semiconductor substrate to be a channel region, and the main table
Surface and are formed in the semiconductor substrate at a distance from each other.
Source of the first conductivity type having high impurity density
Regions and drain regions formed in the semiconductor substrate.
And a bottom surface of at least a part of a side surface of the source region.
Second-conductivity-type semiconductor region having high impurity density
And one end touches or overlaps the source region,
A gate formed so that the other end extends into the channel region.
Gate insulating film and a gate formed on the gate insulating film
An electrode, and the electrode at the upper end of the semiconductor region
The depth from the main surface is the main surface in the drain region.
Is formed shallower than the depth from the surface, and the edge of the semiconductor region
A portion of the drain region over the edge of the source region.
It is formed to project.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

As shown in FIG. 1 (a), M of the present invention is used.
The OSSIT 100 is composed of an n-type low impurity density semiconductor substrate 11 serving as a channel region, a p-type high impurity density semiconductor region 12 provided on the semiconductor substrate 11, and an n-type n-type provided on the semiconductor region 12. And a high impurity density source region 13, an n-type high impurity density drain region 14 provided on the semiconductor substrate 11, and a gate insulating film 15 provided on the channel region so as to be located near the source region 13. And a gate electrode 16 provided on the gate insulating film 15.

Here, the semiconductor region 12 is provided in contact with at least the bottom surface of the source region 13 in order to eliminate a current component that cannot be controlled by the gate. The gate insulating film 15 is provided on the channel region and the source region 13 so as to be in contact with or overlap with the source region 13. Note that the gate electrode 16 is set to the minimum necessary for controlling the potential barrier in the vicinity of the source so that a large electric field is applied only in the vicinity of the drain and the potential barrier in the front surface of the source is not easily lowered by the two-dimensional effect of the gate electrode. It is desirable to provide it.

FIG. 2B is a diagram showing a one-dimensional energy band in the direction perpendicular to the channel near the source region in the MOSSIT 100 (corresponding to XX 'in FIG. 1A). In the figure, region 11 is an n-type doped channel region, region 15 is a gate insulating film, region 16 is a gate electrode, solid line 1 is the bottom of the conduction band, solid line 2 is the top of the valence band, and dotted line. 3 represents the center of the forbidden band, and broken line 4 represents the Fermi level of the channel region. As is clear from the solid line 1, the portion with the lowest energy for electrons is formed inside the channel. This is because the depletion layer spreads from both sides in the n-type doped channel region 11 due to the gate voltage and the diffusion potential of the p-type semiconductor region 12. In order to cut off the flowing current, the depth of the source region 13 is optimized so that the depletion layer spreads completely in the n-type doped semiconductor region 11. Of course, if a reverse bias is applied to the semiconductor region 12, the depletion layer can be spread over a wider area.
The depth of can be set deeply.

FIG. 1C shows 1 in the direction perpendicular to the channel near the drain region (corresponding to YY 'in FIG. 1A).
It is the figure which showed the dimensional energy band. The reference numerals in the figure are the same as those in FIG. According to the figure, it can be seen that in the vicinity of the drain region, a portion having a low potential spreads deeper than in the vicinity of the source, and is less susceptible to the influence of electric field concentration on the surface.

FIG. 3D shows a potential distribution in the channel direction in the portion where the potential inside the channel is the lowest (Z in FIG. 3A).
(Corresponding to -Z '). In the figure, a region 13 is a source region, a region 11 is a channel region, and a region 14 is a drain region. According to the figure, a potential barrier is formed on the front surface of the source region, and the drain voltage is relatively evenly applied to the entire channel. Therefore, the potential barrier on the front surface of the source can be effectively controlled not only by the gate voltage but also by the drain voltage, and a large driving capability can be obtained.

In the MOSSIT 100, the drain-channel-source has an n ⁺ -n ^-- n ⁺ structure so that the drain voltage is not shielded by forming an inversion layer on the surface of the channel region. Also, MOSSI
The maximum current that can be passed at T100 is n ⁺ -n ^-- n
⁺ It is considered to be determined by the structure. n ⁺ −n ⁻ −
In the n ⁺ structure, as the channel length becomes shorter, the density of electrons in the n ⁻ region increases due to the seeping of electrons from the n ⁺ region even in a low electric field. For example, if the electron density at the center of the n ⁻ region is N ₀ , it is expressed as N ₀ = (2π ² ε ₀ ε _si kT) / (q ² L ² ). Where ε ₀ is the permittivity in vacuum, ε _si is the relative permittivity of silicon, k is the Boltzmann constant, T is the absolute temperature, q is the charge of electrons, and L is the length of the n ⁻ region (channel). . A current that is approximately proportional to the electron density flows.
When the drain electric field is further increased, electrons are injected into the channel, the electron density is increased, and the space charge limited current flows.

Further, in order to control the drain current with certainty, it is possible to deplete the gate, including the amount of electrons oozing out from the n ⁺ region and the amount of space charge injected into the channel at a desired channel length and drain voltage. To determine the source depth. Since there is almost no lateral electric field in the vicinity of the top of the potential barrier formed in the channel, it can be considered to be in an almost equilibrium state. Therefore, the maximum voltage that can be applied to the gate reaches a surface potential such that an inversion layer is formed on the surface of the n-type channel region, and the depletion layer cannot be expanded any further. This maximum depletion layer width W _max is n
If the Fermi potential of the type channel region is φ _F , then W _max = {2ε ₀ ε _si (2φ _F ) / qN ₀ }
It can be expressed as ^1/2 . However, N ₀ is the electron density in the center of the channel at the desired channel length and drain voltage, and W _max decreases in proportion to the square root of the electron density N ₀ . From this relationship, the depth of the source region can be calculated within the range in which the n-type channel region is completely depleted.

Here, when expressed as kT / q = β, W _max = L / π (2φ _F / β) ^1/2 The value of φ _F is n-type doped semiconductor region 11
However, it is in the range of β to 20β. Therefore, W _max is approximately equal to L and is 0.5 L at most.
It is about 2 L. The depth of the source region is designed to be shallower than this.

Further, FIG. 2 shows a typical relation between drain current and drain voltage of the MOSSIT 100 of the present invention. Each solid line is a characteristic with respect to a different gate voltage, and shows an unsaturated current-voltage characteristic. Each dashed line is for comparison
It shows an example of the relationship between the drain current and the drain voltage of the conventional MOSFET. As is clear from the figure, in the MOSSIT 100 of the present invention, since the drain current does not show a saturation tendency, a large driving ability can be obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment according to the present invention will be described with reference to FIG. As shown in FIG.
Reference numeral 110 denotes a p-type low-impurity-density semiconductor substrate 10, an n-type low-impurity-density channel region 11 provided on the semiconductor substrate 10, and a p-type channel provided in the channel region 11.
Type semiconductor region 12 having a high impurity density, and the semiconductor region 1
N-type source region 13 of high impurity density provided on
An n-type drain region 14 having a high impurity density provided in the channel region 11, a gate insulating film 15 provided on a part of the surface of the channel region so as to be in contact with the source region 13, and on the gate insulating film 15. And a gate electrode 16 provided on the.

In the MOSSIT 110, the gate electrode 16 is formed on the channel region 11 on the source region 13 side from the central portion of the channel region 11. The position of the potential barrier on the front surface of the source is the center of the channel region 11 when the drain voltage is not applied, and is located on the source side with respect to this when the drain voltage is applied. Therefore, it is desirable that the length of the gate electrode 16 be at least half the length of the channel region 11 or less. Further, the semiconductor region 12 for preventing a current flowing in a deep portion that cannot be controlled by the gate is formed so that its end is closer to the drain region 14 than the end of the source region 13. Like the gate electrode 16, this semiconductor region 12 is also preferably overhanged by half or less of the length of the channel region 11 in order to avoid a two-dimensional effect. The depth of the source region 13 is shallower than the depth of the drain region 14, and prevents a current flowing in a deep portion that cannot be controlled by the gate.

The impurity density of the channel region 11 is 10 ¹¹
It is about 10 ¹⁸ cm ⁻³ and is formed by ion implantation, thermal diffusion method or epitaxial growth method. The source region 13 and the drain region 14 are formed by an ion implantation method or a thermal diffusion method and have an impurity density of 10 ¹⁹ to.
10 ²¹ cm ⁻³ , diffusion depth is 0.05 to 0.5 μ
It is about m. The impurity density of the semiconductor region 12 is 10 ¹⁷
It is about 10 ¹⁹ cm ⁻³ and is formed by ion implantation or the like. A thin silicon oxide film is often used as the gate insulating film 15, and the film thickness is about 1.5 nm to 100 nm. The material of the insulating film is not limited to the thermal oxide film, but may be a composite film of an oxide film and a nitride film. The gate electrode 16 is, for example, a polycrystalline silicon film doped with impurities at a high concentration, and has a film thickness of about 100 nm to 500 nm. Needless to say, a high melting point metal or a high melting point metal silicide may be laminated on polycrystalline silicon, or a metal film may be used. Although not shown, an insulating film is formed on the source region 13 and the drain region 14, and an electrode is provided through each contact hole and connected to a metal wiring such as Al.

Furthermore, a modification of the first embodiment is shown in FIG.
More will be described. The same parts as MOSSIT 110 are omitted. In MOSSIT 120, the gate electrode 16 is formed on the entire surface of the channel region 11. Source region 13
A gate oxide film is formed on the channel region 11 near the channel region 11, and a thick oxide film 17 is formed on the channel region 11 near the drain region 14. Therefore, the gate electrode 16
Even if formed over the entire channel region 11, the MOSSIT
You can get the same effect as 110.

According to such a structure, the potential barrier on the front surface of the source can be effectively controlled not only by the gate voltage but also by the drain voltage, and the drain current according to the exponential function law can be flowed over a wide range. Therefore, a transistor with high driving capability can be obtained.

[0028] The second embodiment according to the present invention FIGS. 4 (a)
Will be described with reference to. MOSSIT 130 is a channel
An n-type semiconductor substrate 22 of low impurity density,
The p-type provided on the conductor substrate 22 has a relatively high impurity density.
The semiconductor region 23 and the semiconductor provided in the semiconductor region 23.
Source region 13 and the drain provided on the semiconductor substrate 22.
The channel region is overlapped with the region 14 and the source region 13.
A gate insulating film 15 provided on a part of the surface of the region,
And a gate electrode 16 provided on the gate insulating film 15.
To do. In MOSSIT 130, the substrate is an n ^- type half
Since the conductor substrate 22 is used, the side surface of the source region 13
Region of p ⁺ type that is in contact with at least a part of the
Area 23 is formed. This semiconductor region 23 is, for example, an ion
It can be formed by implantation, and can be formed by normal ion implantation.
N-type channel region (semiconductor
It can be formed by protruding to the substrate 22).

Further, a reference example related to the second embodiment will be described with reference to FIG. MOSSIT140
Is a p-type semiconductor substrate 21 having a relatively high impurity density, and
Of n-type and low impurity density provided on the semiconductor substrate 21 of
Channel region 11 and n-type provided on semiconductor substrate 21
And the high impurity density source region 13 and the channel region 11
N-type drain region 14 of high impurity density provided in
Of the channel region surface so as to overlap with the source region 13.
The gate insulating film 15 provided on a part of the gate insulating film 15 and the gate insulating film 15
And a gate electrode 16 provided on the edge film 15. This
In the MOSSIT 140, the side surface of the source region 13 is small.
At least one part and the bottom should be in contact with the semiconductor substrate 21.
Formed on the surface and cannot be controlled by the gate at the part away from the interface.
Control the current. In addition, the source region 13 is formed on the semiconductor substrate
21 is provided in the source region 13 and the drain
The diffusion depths of the regions 14 can be the same.

In each of the MOSSITs 130 and 140, the p ⁺ region (semiconductor substrate 21 and semiconductor region 23) surrounding the side surface of the source region 13 projects to the drain side , but the projection is the same as the potential of the gate electrode 16. It is the extent to which a barrier is formed.

[0031] The third embodiment according to the present invention FIGS. 5 (a)
Will be described with reference to. The MOSSIT 150 includes a p-type low-impurity-density semiconductor substrate 10 and an n-type low-impurity-density channel region 11 provided on the semiconductor substrate 10.
A p-type semiconductor region 12 having a high impurity density, which is provided on the semiconductor substrate 10 so as to be in contact with the channel region 11;
A groove 24 (U-shaped) provided in the channel region 11,
The source region 13 provided on the semiconductor region 12, the drain region 14 provided on the channel region 11 from the side wall and bottom of the groove 24, and the gate insulating film provided on a part of the surface of the source region 13 and the channel region 11. 15,
And a gate electrode 16 provided thereon.

The semiconductor region 12 is in contact with the bottom surface of the source region 13, and the end of the semiconductor region 12 extends beyond the end of the source region 13 toward the drain side. Needless to say,
The semiconductor region 12 prevents a current flowing in a deep portion that cannot be controlled by the gate. Further, in the MOSSIT 150, since the groove 24 is provided, the deep drain region 14 and the shallow source region 13 can be simultaneously formed in one ion implantation step. Particularly, if the oblique implantation is performed, the drain region on the sidewall of the groove 24 can be easily formed.

Further, a reference example related to the third embodiment will be described with reference to FIG. The same parts as MOSSIT150 are omitted. The MOSSIT 160 includes a semiconductor substrate 10, a channel region 11 provided on the semiconductor substrate 10, and the semiconductor substrate 1 so as to be in contact with the channel region 11.
0, a semiconductor region 12 provided on the semiconductor region 12, a source region 13 provided on the semiconductor region 12, a drain region 14 provided on the semiconductor substrate 10 so as to be adjacent to the channel region 11, and a sidewall of the source region 13. And a gate insulating film 15 provided on the surface of the channel region 11 and the following,
And a gate electrode 16 provided on the gate insulating film 15. The channel region 11 is exposed by the groove portion 24, the bottom surface of the source region 13 is in contact with the semiconductor region 12, a part of the side surface thereof is the side wall of the groove portion 24, and the other part of the side surface is the channel region 11. It is a contact structure.

In this MOSSIT 160, the source region 13 is formed by ion implantation or the like, and at the same time, the drain region 14 is formed by ion implantation or the like into the channel region 11 from a part of the bottom surface of the groove 24 provided in the channel region 11. However, since the source region 13 has a structure in which a part of the side surface is in contact with the channel region 11, even if the source region 13 is formed at the same time as the drain region 14, a source region that is substantially shallower by the depth of the groove 24 is formed. Can be formed. Moreover,
Since a thin gate electrode can be left on the side wall of the groove 24 by using a technique such as reactive ion etching, there is an advantage that a short gate electrode can be formed only near the source.

[0035] The first reference example definitive to the present invention will be described with reference to FIG. The MOSSIT 170 is in contact with the source region 13 and the n-type and low-impurity-density channel region 11, and the n-type and high-impurity-density source region 13 and drain region 14 respectively provided so as to face each other with the channel region 11 interposed therebetween. Channel region 1 so that it overlaps
A part of the other surface of the channel region 11 so as to face the gate insulating film 15a and the gate electrode 16a provided on the gate insulating film 15a and the gate insulating film 15a and the gate electrode 16a. It has a gate insulating film 15b and a gate electrode 16b provided thereon.

In MOSSIT 170, the channel region 11
The gate oxide films 15a and 15b and the gate electrodes 16a and 16b are formed on both surfaces facing each other. This structure does not necessarily require the p-type semiconductor region having a high impurity density, which is in contact with the bottom surface of the source region as in the above-described embodiments. It suffices if the width of the channel region sandwiched between the two gate electrodes is within a range that can be controlled by the gate electrodes.

The MOSSIT 170 having such a structure
Can be formed on an insulating substrate or the like. As a matter of course, a plug is formed on the surface of the semiconductor substrate by using a reactive ion etching technique or the like to form an n ⁺ −n ⁻ −n ⁺ structure in the vertical direction, and a gate electrode is wound around the structure. Is also good.

[0038] The second reference example definitive to the present invention will be described with reference to FIG. According to FIG. 3A, MOSSIT1
Reference numeral 80 denotes an n-type high impurity density semiconductor substrate 25 (hereinafter referred to as drain region 25) which becomes a drain region, and an n-type low impurity density channel region 11 provided on a part of the surface of the drain region 25. , A p-type semiconductor region 12 having a high impurity density provided in the central portion on the channel region 11.
And an n-type source region 13 of high impurity density provided on the channel region 11 so as to be located around the semiconductor region 12, and provided on a part of the surface of the source region 13 and the channel region 11. It has a gate insulating film 15 and a gate electrode 16.

In MOSSIT 180, the drain region 25
-Channel region 11-The source region 13 is formed in the vertical direction, and the gate insulating film 15 and the gate electrode 16 are wound around the source region 13 and the channel region 11. As shown in the figure, even if the diameter of the plug (channel region 11 portion) is large, by providing the semiconductor region 12 at the center for suppressing the current that cannot be controlled by the gate, both the gate and the drain are provided. The drain current can be controlled with. In the figure, the semiconductor region 12
Although the depth of is formed to be slightly deeper than that of the source region 13, the depth may be the same.

Further, a modified example of the second reference example will be described with reference to FIG. Only points different from the MOSSIT 180 will be described. The MOSSIT 190 includes a drain region 25, a convex channel region 11, a source region 13 provided on the tip of the channel region 11,
The gate insulating film 15 and the gate electrode 16 are provided around the source region 13 and the cutout portion of the channel region 11. In the MOSSIT 190, it is not necessary to form the semiconductor region 12 required in the MOSSIT 180 by changing the thickness of the channel region 11 on the way.

As described above, even if the drain-channel-source is formed in the vertical direction, the same effect as that of the first embodiment can be obtained by forming it on the channel region near the source region. Further, for example, the effect obtained from the shallow diffusion depth of the source region described in the first embodiment is that the semiconductor region 12 is formed in the center of the plug or the plug is formed in a convex shape in the fifth embodiment. It can be realized.

In addition, the MO according to the embodiment and the reference example
The maximum current that can flow in SSIT 100 to 190 is n
It is considered to be determined by the ⁺ −n ⁻ −n ⁺ structure.
That is, when a voltage is applied to the drain and the density of electrons in the channel increases, the potential distribution is determined by this space charge and the space charge limiting current flows. Therefore, as will be described later, by controlling the distribution of space charges in the vicinity of the drain by another gate electrode linked to the drain voltage, a larger current can be flown.

Hereinafter, MOSSIT100 and MOSSIT
Taking 170 as an example, a MOSSIT having another gate electrode linked to the drain voltage will be described.

[0044] The third reference example definitive to the present invention will be described with reference to FIG. As shown in FIG.
The SIT 200 is composed of an n-type low impurity density semiconductor substrate (hereinafter referred to as a channel region) 11 which also serves as a channel region, a p-type high impurity density semiconductor region 12 provided in the channel region 11, and a semiconductor region 12 on the semiconductor region 12. An n-type high impurity density source region 13 provided in the channel region 11, an n-type high impurity density drain region 14 provided in the channel region 11,
The channel region 1 is located near the source region 13.
1, a gate insulating film 15 provided on a part of the channel region 11, a gate electrode 16 provided on the gate insulating film 15, and a gate provided on a part of the channel region 11 so as to be located in the vicinity of the drain region 14. It has an insulating film 17 and a gate electrode 18 provided on the gate insulating film 17. The gate insulating film 17 and the gate electrode 18 are the drain region 1
4 is formed so as to be in contact with or overlap with 4. A gate voltage V _G1 is applied to the gate electrode 16 and the gate electrode 1
A voltage V _{G2, which} is approximately the same as the drain voltage V _D , is applied to 8.

Further, a modification of the third reference example will be described with reference to FIG. Only the points different from MOSSIT 200 will be described. The MOSSIT 210 includes a channel region 11, a semiconductor region 12 provided in the channel region 11, and a source region 1 provided on the semiconductor region 12.
3 and the drain region 14 provided in the channel region 11
A gate insulating film 15 provided on a part of the channel region 11 so as to be located near the source region 13, a gate electrode 16 provided on the gate insulating film 15, and a position near the drain region 14. Channel region 1
1 and a gate insulating film 17 provided on a portion of the gate insulating film 1
7 and a gate electrode 19 provided on the gate electrode 7.

[0046] The fourth reference example definitive to the present invention will be described with reference to FIG. According to FIG. 7A, MOSSIT2
Reference numeral 20 denotes a channel region 11, a semiconductor region 12 provided in the channel region 11, a source region 13 provided on the semiconductor region 12, a drain region 14 provided in the channel region 11, and a channel region 11 on the channel region 11. The gate insulating film 20 provided on the gate insulating film 20, the gate electrode 18 provided on a part of the gate insulating film 20 so as to be located near the drain region 14, and the gate insulating film 20 located near the source region 13. And a gate electrode 16 which is provided on a part of the gate electrode 18 and overlaps with the gate electrode 18 at one end through an insulating film. A gate voltage V _G1 is applied to the gate electrode 16, and a voltage V _{G2 that} is approximately the same as the drain voltage V _D is applied to the gate electrode 18.

Further, a modification of the fourth reference example will be described with reference to FIG. Only the points different from the MOSSIT 220 will be described. The MOSSIT 230 includes a channel region 11, a semiconductor region 12 provided in the channel region 11, a source region 13 provided on the semiconductor region 12, and a drain region 1 provided in the channel region 11.
4 and the gate insulating film 2 provided on the channel region 11
0, and the gate electrode 1 provided on a part of the gate insulating film 20 so that one end thereof is directly connected to the drain region (electrode) 14 and is located in the vicinity of the drain region 14.
9 and a gate electrode 16 provided on a part of the gate insulating film 20 so as to be located in the vicinity of the source region 13 and having one end thereof overlapping the gate electrode 19 with the insulating film interposed therebetween.

[0048] The fifth reference example definitive to the present invention will be described with reference to FIG. 10. As shown in FIG.
The SIT 240 is an n-type low impurity concentration channel region 1
1, a source region 13 and a drain region 14 each having an n-type and a high impurity density, which are provided so as to face each other with the channel region 11 interposed therebetween, a gate insulating film 20a provided on the surface of the channel region 11, and A gate insulating film 20b provided on the other surface of the channel region 11 so as to face the gate insulating film 20a, and a gate electrode provided on a part of the gate insulating film 20a so as to be located in the vicinity of the drain region 14. 18a, a gate electrode 16a provided in the vicinity of the source region 13 and provided on a part of the gate insulating film 20a so that one end thereof overlaps with the gate electrode 18a via the insulating film, and the gate electrode 18a and the gate electrode 16a. And a gate electrode 18b and a gate electrode 16b provided on the gate insulating film 20b so as to face each other.

Further, a modification of the fifth reference example will be described with reference to FIG. Only the points different from MOSSIT 240 will be described. The MOSSIT 250 includes a channel region 11, a source region 13 and a drain region 14 which are provided so as to sandwich the channel region 11, respectively.
A gate insulating film 20a and a gate insulating film 20b respectively provided on the surface of the channel region 11 and the other surface,
The gate insulating film 20a is directly connected to the drain region (electrode) 14 and is located near the drain region 14.
Of the gate electrode 19a provided on a part of the
9a so that the gate insulating film 20a overlaps with the insulating film 9a.
Has a gate electrode 16a provided on a part thereof, and a gate electrode 19a and a gate electrode 19b and a gate electrode 16b provided on the gate insulating film 20b so as to face the gate electrode 19a and the gate electrode 16a.

As described in the third to fifth reference examples, in addition to the gate electrode provided in the vicinity of the source region, another gate electrode is provided in the vicinity of the drain region to control the drain electric field. It is possible to obtain a larger driving ability. In addition, MOSSIT100,1
Even if the structure is other than 70, the effect of having another gate electrode is the same.

Although the n-channel insulated gate type static induction transistor has been described so far, the present invention is not limited to this, and the same applies to the p-channel insulated gate type static induction transistor.

[0052]

According to the MOSSIT of the present invention, the potential barrier on the front surface of the source can be effectively controlled not only by the gate voltage but also by the drain voltage, and a large driving capability can be obtained. Further, unlike a conventional MOSFET, a large electric field is not applied only in the vicinity of the drain, so that the resistance to hot carriers is high, and since no current is passed to the semiconductor-insulating film interface, it is less affected by interface traps, etc., and has low noise. It has the characteristics of. It is possible to provide an insulated gate static induction transistor having a large driving capability and high reliability, and its industrial value is great.

[Brief description of drawings]

FIG. 1A is a schematic sectional view of a MOSSIT 100 according to the present invention, and FIG. 1B is a cross-sectional view taken along line X- in FIG.
It is a figure which shows the electric potential distribution along X ', (c) is a electric potential distribution map along YY' in the same figure (a), (d)
FIG. 4 is a diagram showing a potential distribution along ZZ ′ in FIG.

FIG. 2 is a diagram showing a relationship between a drain current and a drain voltage (solid line) of a MOSSIT 100 and a relationship between a drain current and a drain voltage of a MOSFET (broken line).

FIG. 3 (a) is a schematic cross-sectional view of a MOSSIT 110 according to the present invention, and FIG. 3 (b) is a MOS according to the present invention.
It is sectional drawing which shows SIT120 typically.

4A is a schematic cross-sectional view of a MOSSIT 130 according to the present invention, and FIG. 4B is a schematic cross-sectional view of a MOSSIT 140 according to a related reference example .

5A is a schematic sectional view of a MOSSIT 150 according to the present invention, and FIG. 5B is a schematic sectional view of a MOSSIT 160 according to a related reference example .

FIG. 6 is a reference example definitive to the present invention MOSSIT17
It is sectional drawing which shows 0 as a model.

7 (a) is a reference example definitive the present invention MOSS
IT180 is a cross-sectional view schematically illustrating the, (b) is a sectional view showing a MOSSIT190 a reference example definitive the present invention schematic manner.

8 (a) is a reference example definitive the present invention MOSS
IT200 is a cross-sectional view schematically illustrating the, (b) is a sectional view showing a MOSSIT210 a reference example definitive the present invention schematic manner.

9 (a) is a reference example definitive the present invention MOSS
IT220 is a cross-sectional view schematically illustrating the, (b) is a sectional view showing a MOSSIT230 a reference example definitive the present invention schematic manner.

[10] (a) MOS is a reference example definitive to the present invention
SIT240 a cross-sectional view schematically illustrating the, (b) is a sectional view showing a MOSSIT250 a reference example definitive the present invention schematic manner.

FIG. 11 is a diagram showing a relationship between a drain current and a drain voltage of a MOSFET.

FIG. 12 is a diagram showing the relationship between the drain current and drain voltage of SIT.

FIG. 13 is a sectional view schematically showing a conventional MOSSIT.

FIG. 14 shows characteristics of a conventional MOSSIT,
(A) is the figure which showed the relationship of the drain current with respect to drain voltage using logarithm, (b) is the figure which showed the relationship of the drain current with respect to gate voltage using logarithm.

Continuation of the front page (56) Reference JP-A-57-211276 (JP, A) JP-A-55-55569 (JP, A) JP-A-54-125986 (JP, A) JP-A-54-51784 (JP , A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 301 H01L 29/80

Claims (3)

(57) [Claims] 1. A source / drain region of a second conductivity type formed on a main surface of a semiconductor substrate of a first conductivity type and having a high impurity density, respectively, and the source region and the drain region on the main surface. A second conductivity type channel region having a low impurity density, a first conductivity type semiconductor region having a high impurity density and being in contact with the bottom surface of the source region and having one end in contact with the source region; formed as <br/> Do heavy Ri and the other end extends into the channel region
And a gate insulating film formed on the gate insulating film.
A gate electrode and a surface in the source region
Is the depth from the surface in the drain region.
The semiconductor region is shallower than the
So that it overhangs the drain region rather than the end of the drain region.
An insulated gate static induction transistor characterized by being formed . 2. A semiconductor substrate of a first conductivity type, which has a main surface and serves as a channel region having a low impurity density,
A source region and a drain region of the first conductivity type, which are formed on the main surface and spaced apart from each other in the semiconductor substrate, and have high impurity densities; and a side surface of the source region formed in the semiconductor substrate . At least in part and
The second conductivity type semiconductor region having a high impurity density is in contact with the bottom surface , and one end is in contact with or overlaps with the source region.
And the other end is formed to extend to the channel region.
A gate insulating film and a gate electrode formed on the gate insulating film .
The depth from the main surface is equal to the depth in the drain region.
The semiconductor region is formed to be shallower than the depth from the main surface.
The edge of the drain region is more than the edge of the source region.
An insulated gate static induction transistor, characterized in that it is formed so as to overhang . 3. From the main surface in the source region
Depth from the main surface in the drain region
Insulated gate static induction transistor according to claim 2, wherein the A is the same.