JP2780175B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2780175B2 JP2780175B2 JP63174126A JP17412688A JP2780175B2 JP 2780175 B2 JP2780175 B2 JP 2780175B2 JP 63174126 A JP63174126 A JP 63174126A JP 17412688 A JP17412688 A JP 17412688A JP 2780175 B2 JP2780175 B2 JP 2780175B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gate electrode
- groove
- diffusion layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 description 12
- 239000010410 layer Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は電界効果トランジスタのゲート構造に関す
る。The present invention relates to a gate structure of a field effect transistor.
［従来の技術］ 従来、林豊：“ギガビット級の集積度にかける夢",日
本の科学と技術,27,242,pp,46−47（昭61）に示され
た、第２図の如き電界効果トランジスタの提案はあっ
た。すなわち、ガラス等の基板11の表面には層間絶縁膜
17を介して、第１のゲート電極16、次で第１のゲート酸
化膜15、次で半導体Si膜12と該半導体Si膜12にソース拡
散層13とドレイン拡散層14が形成され、更にその上に第
２のゲート酸化膜15′、及び第２のゲート電極16′が形
成されて成る。[Conventional technology] Conventionally, Yutaka Hayashi: "Dream for Gigabit-class integration", Field effect as shown in Fig. 2 shown in Japanese Science and Technology, 27, 242, pp. 46-47 (Showa 61) There was a proposal for a transistor. That is, an interlayer insulating film is formed on the surface of the substrate 11 such as glass.
A first gate electrode 16, a first gate oxide film 15, a semiconductor Si film 12, and a source diffusion layer 13 and a drain diffusion layer 14 are formed on the semiconductor Si film 12 via the first gate electrode 16. A second gate oxide film 15 'and a second gate electrode 16' are formed thereon.
［発明が解決しようとする課題］ しかし、上記従来技術によると、多層膜構造をとらね
ばならず、又、半導体膜を結晶欠陥なしに作成するのが
困難であり、ひいては、素子特性のリーク電流が増大す
ると云う課題があった。[Problems to be Solved by the Invention] However, according to the above-mentioned conventional technology, it is necessary to take a multilayer film structure, and it is difficult to form a semiconductor film without crystal defects. There is a problem that increases.
本発明は、かかる従来技術の課題を解決し、単結晶半
導体基板を用いて２つのゲートでチャネル層を制御する
電界効果トランジスタ構造を提供する事を目的とする。An object of the present invention is to solve the problems of the prior art and to provide a field effect transistor structure in which a channel layer is controlled by two gates using a single crystal semiconductor substrate.
［課題を解決するための手段］ 上記課題を解決するために、本発明の半導体装置は、
半導体基板中に離間して設けられた第１の溝及び第２の
溝、前記第１の溝の内壁に設けられた第１ゲート絶縁
膜、前記第２の溝の内壁に設けられた第２ゲート絶縁
膜、前記第１の溝に埋置した第１ゲート電極、前記第２
の溝に埋置した第２ゲート電極、前記第１ゲート電極と
前記第２ゲート電極に挟まれた前記半導体基板中に設け
られたチャネル領域を有する半導体装置であって、前記
第１ゲート電極又は前記第２ゲート電極をシールド電極
とすることを特徴とする。[Means for Solving the Problems] In order to solve the above problems, a semiconductor device of the present invention
A first groove and a second groove provided separately in a semiconductor substrate, a first gate insulating film provided on an inner wall of the first groove, and a second gate provided on an inner wall of the second groove. A gate insulating film, a first gate electrode embedded in the first groove, the second gate electrode,
A semiconductor device having a second gate electrode buried in a trench, a channel region provided in the semiconductor substrate sandwiched between the first gate electrode and the second gate electrode, wherein the first gate electrode or The second gate electrode is a shield electrode.
［実施例］ 以下、実施例により本発明を詳述する。EXAMPLES Hereinafter, the present invention will be described in detail with reference to examples.
第１図は、本発明の一実施例を示す２つのトレンチ・
ゲートを有するMOS型トランジスタの断面図である。す
なわち、Si基板１の表面から第１及び第２のゲート電極
3,3′と、ゲート酸化膜2,2′とから成るトレンチ・ゲー
トと、誘電体から成るアイソレーション４が形成され、
前記２つのトレンチ・ゲート間のチャネル６の上下にド
レイン拡散層８及びソース拡散層８と連らなった埋め込
み拡散層７を形成してソースとなしたものである。本例
による各部寸法例は、チャネル６の巾は、0.1μｍ以下
であり、長さ（深さ方向）は0.02μｍ程度となる。ゲー
ト2,2′の巾は0.1μｍ以下であり、深さは0.3μｍ以下
となる。ゲート酸化膜2,2′の厚さは20Å程度となり、
拡散層５の深さは0.1μｍ以下である。アイソレーショ
ン４の寸法はトレンチ・ゲートと同様深さ0.3μｍ以
下、巾0.1μｍ以下程度となる。いずれも寸法的にはＸ
線露光やドライ・エッチング及び拡散，酸化処理により
達成することができる。FIG. 1 shows two trenches illustrating one embodiment of the present invention.
FIG. 2 is a cross-sectional view of a MOS transistor having a gate. That is, the first and second gate electrodes from the surface of the Si substrate 1
3, 3 ', a trench gate composed of gate oxide films 2, 2' and an isolation 4 composed of a dielectric are formed.
A buried diffusion layer 7 connected to the drain diffusion layer 8 and the source diffusion layer 8 is formed above and below the channel 6 between the two trenches and the gate to serve as a source. In the example of the dimensions of each part according to the present example, the width of the channel 6 is 0.1 μm or less, and the length (in the depth direction) is about 0.02 μm. The width of the gates 2, 2 'is 0.1 μm or less, and the depth is 0.3 μm or less. The thickness of the gate oxide films 2, 2 'is about 20 mm,
The depth of the diffusion layer 5 is 0.1 μm or less. The dimensions of the isolation 4 are about 0.3 μm or less in depth and about 0.1 μm or less in width similarly to the trench gate. Both are dimensionally X
It can be achieved by line exposure, dry etching, diffusion and oxidation treatment.
［発明の効果］ 本発明による２つのゲートを有するMOSFET（Dual Gat
e MOS FET）では、短チャネル長効果、サブスレッショ
ルド効果を減少させることができると共に、一方にゲー
トによるシールド効果、チャネル領域のシリコン巾を薄
くすることによる微細化効果によるチャネル長の0.02μ
ｍ程度化が出来ると共に、単結晶Siを用いる事により結
晶欠陥を無くして、リーク電流を減少できる効果があ
る。[Effect of the Invention] A MOSFET (Dual Gat) having two gates according to the present invention
e MOS FET) can reduce the short channel length effect and the sub-threshold effect, and on the other hand, the gate shield effect and the channel length of 0.02μ due to the miniaturization effect by reducing the silicon width of the channel region.
The use of single crystal Si has the effect of eliminating crystal defects and reducing the leakage current.
第１図は本発明の一実施例を示す２ゲートMOS FETの断
面図であり、第２図は従来技術による２ゲートMOS FET
の断面図である。 １……Si基板 2,2′……ゲート酸化膜 3,3′……第1,第２ゲート電極 ４……アイソレーション ５……ソース拡散層 ６……チャネル ７……埋め込み拡散層 ８……ドレイン拡散層 11……基板 12……Si膜 13……ソース拡散層 14……ドレイン拡散層 15,15′……ゲート酸化膜 16,16′……第1,第２ゲート電極 17……層間絶縁膜 Ｓ……ソース Ｄ……ドレイン G1，G2……第1,第２ゲートFIG. 1 is a sectional view of a two-gate MOS FET showing an embodiment of the present invention, and FIG. 2 is a conventional two-gate MOS FET.
FIG. 1 ... Si substrate 2,2 '... Gate oxide film 3,3' ... First and second gate electrodes 4 ... Isolation 5 ... Source diffusion layer 6 ... Channel 7 ... Buried diffusion layer 8 ... ... Drain diffusion layer 11 ... Substrate 12 ... Si film 13 ... Source diffusion layer 14 ... Drain diffusion layer 15,15 '... Gate oxide film 16,16' ... First and second gate electrodes 17 ... interlayer insulating film S ...... source D ...... drain G 1, G 2 ...... first, second gate
Claims (1)
溝及び第２の溝、前記第１の溝の内壁に設けられた第１
ゲート絶縁膜、前記第２の溝の内壁に設けられた第２ゲ
ート絶縁膜、前記第１の溝に埋置した第１ゲート電極、
前記第２の溝に埋置した第２ゲート電極、前記第１ゲー
ト電極と前記第２ゲート電極に挟まれた前記半導体基板
中に設けられたチャネル領域を有する半導体装置であっ
て、 前記第１ゲート電極又は前記第２ゲート電極をシールド
電極とすることを特徴とする半導体装置。A first groove and a second groove provided apart from each other in a semiconductor substrate; and a first groove provided on an inner wall of the first groove.
A gate insulating film, a second gate insulating film provided on an inner wall of the second groove, a first gate electrode embedded in the first groove,
A semiconductor device having a second gate electrode buried in the second groove, a channel region provided in the semiconductor substrate between the first gate electrode and the second gate electrode, A semiconductor device, wherein the gate electrode or the second gate electrode is a shield electrode.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174126A JP2780175B2 (en) | 1988-07-12 | 1988-07-12 | Semiconductor device |
| KR1019890007221A KR0173111B1 (en) | 1988-06-02 | 1989-05-30 | Trench gate metal oxide semiconductor field effect transistor |
| US07/360,486 US5142640A (en) | 1988-06-02 | 1989-06-02 | Trench gate metal oxide semiconductor field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174126A JP2780175B2 (en) | 1988-07-12 | 1988-07-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0223668A JPH0223668A (en) | 1990-01-25 |
| JP2780175B2 true JP2780175B2 (en) | 1998-07-30 |
Family
ID=15973109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63174126A Expired - Lifetime JP2780175B2 (en) | 1988-06-02 | 1988-07-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780175B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230905C (en) * | 2001-04-26 | 2005-12-07 | 株式会社东芝 | Semiconductor device |
| DE10231966A1 (en) * | 2002-07-15 | 2004-02-12 | Infineon Technologies Ag | Field effect transistor used as control transistor comprises a doped channel region, doped connecting regions, a control region, and an electrical insulating region arranged between the control region and the channel region |
| KR100607177B1 (en) | 2004-04-06 | 2006-08-01 | 삼성전자주식회사 | A semiconductor device including a transistor having asymmetric channel region and a method of fabricating the same |
| US7936009B2 (en) * | 2008-07-09 | 2011-05-03 | Fairchild Semiconductor Corporation | Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6245058A (en) * | 1985-08-22 | 1987-02-27 | Nec Corp | Semiconductor device and its manufacture |
| JPS6381981A (en) * | 1986-09-26 | 1988-04-12 | Toshiba Corp | Sense amplifier and manufacture thereof |
-
1988
- 1988-07-12 JP JP63174126A patent/JP2780175B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0223668A (en) | 1990-01-25 |
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