JPH05315437A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce thermal and electrical interference between elements, in the manufacturing method of a semiconductor device wherein an SOI region is formed by mutual bonding of silicon semiconductor substrates. CONSTITUTION:A first oxide film 12, doped polysilicon 20 and a second oxide film 14 are formed between a first silicon semiconductor substrate 1 and a second silicon semiconductor substrate 2 which are mutually bonded, and an SOI (silicon on insulator) region 10 is constituted. In the SOI region 10 formed in the above manner, a buried oxide film is double-layered and can be thickly formed, so that thermal interference between elements can be reduced. Further, by applying the doped polysilicon 20 to an electric shield, electric interference between elements can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dielectric separable semiconductor device formed in a semiconductor layer (SOI: Silicon On Insulator) on a dielectric film for insulation separation.

[0002]

2. Description of the Related Art Conventionally, CMOS (Compl
As an ementary metal oxide semiconductor), one disclosed in Japanese Patent Laid-Open No. 2-96350, "Method for manufacturing semiconductor device" is known. In addition, JP-A-3-126
The one disclosed in Japanese Unexamined Patent Publication No. 255-255, “Semiconductor Device and Manufacturing Method Therefor” is known. The former is a method of forming an element isolation region, which is isolated by an oxide film, on a semiconductor substrate. In the latter case, polysilicon and CVD (Chemical
Vapor Deposition) A method of forming an SOI by bonding via an oxide film.

[0003]

By the way, the former method is not desirable as an AC isolation characteristic such as substrate potential fluctuation and external noise because it is an oxide film only and does not have an electrical shield layer. It was disadvantageous for noise. In addition, there is a limit to the film thickness in which the oxide film can be embedded, and there is a problem that the SOI region is difficult to separate even when heat is generated from the outside. According to the latter method, in order to bond the silicon wafers with each other by embedding the CVD oxide film, C
A flattening (polishing) step is required after the VD oxide film is embedded, which is troublesome. In addition, it is difficult to set the thickness of the CVD oxide film to 0.5 μm or more from the viewpoint that the bonding strength is weak due to the deterioration of the oxide film quality and the productivity is reduced. There was a problem of being few.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which an SOI region is formed by bonding silicon semiconductor substrates to each other, in a bonding strength. By increasing the thickness of the buried oxide film and providing an electrical shield layer, it is possible to reduce thermal and electrical mutual interference between elements.

[0005]

The structure of the invention for solving the above-mentioned problems is a groove for element isolation on the mirror surface side of the first silicon semiconductor substrate and a recess for isolation from the second silicon semiconductor substrate. A second step of sequentially forming a first oxide film and doped polysilicon by thermal oxidation in the groove and the recess, and a mirror surface side of the first silicon semiconductor substrate and the first step. A third oxide film is formed by bonding the second silicon semiconductor substrate to the mirror surface side and thermally oxidizing the groove and the recess again, and at least the recess is filled with the second oxide film. And a process.

[0006]

According to the above means, the groove and the recess are formed in the first silicon semiconductor substrate, and the first oxide film and the doped polysilicon are sequentially formed in the groove and the recess by thermal oxidation. It Further, the groove and the recess are thermally oxidized and at least the recess is filled with the second oxide film to form the SOI region. In general, the oxide film has a smaller thermal conductivity than that of a silicon semiconductor, so that the inflow of heat from the semiconductor substrate and adjacent elements can be reduced. Furthermore, since a buried oxide film can be formed by thermal oxidation, the bonding reliability can be improved without the need for a polishing step like when forming a CVD oxide film. As described above, in the method for manufacturing a semiconductor device of the present invention, a double oxide film (separation thermal oxide film) is formed by utilizing the thermal oxidation of doped polysilicon, so that the oxide film thickness around the SOI region can be easily adjusted. The thickness can be increased, and thermal mutual interference between elements can be reduced. Further, it is possible to reduce the oxide film capacitance between the SOI region and the semiconductor substrate and between the adjacent elements, and it becomes difficult for the influence of the potential variation due to the semiconductor substrate and the adjacent elements to be transmitted to the SOI region. Further, by connecting the doped polysilicon layer sandwiched by oxide films to a fixed potential such as GND or power supply voltage, this doped polysilicon layer can be used as an electrical shield layer for the substrate and adjacent elements, Electrical mutual interference between elements can be reduced.

[0007]

EXAMPLES The present invention will be described below based on specific examples. FIG. 1 is a schematic view showing a cross-sectional structure of a semiconductor device formed by using the method for manufacturing a semiconductor device according to the present invention. 2 and 3 are schematic views showing a sectional structure in the manufacturing process of the semiconductor device of FIG. The semiconductor device 100 has a mirror surface side of the first silicon semiconductor substrate 1 and a second silicon semiconductor substrate 1.
Is bonded to the mirror surface side of the silicon semiconductor substrate 2.
Then, the first oxide film 12, the doped polysilicon 20 and the second oxide film 14 formed between them form an S
The OI region 10 is formed.

In the apparatus of the present embodiment, CM is placed in the SOI area 10.
The OS is formed, and DMOS (Double Diff
usion MOS: Self-aligned double diffusion MOS) was formed. The CMOS in the SOI region 10 has an S (source) 6
1, G (gate) 62, D (drain) 63 and GND
It is formed of an nchMOS formed of each electrode of (ground) 64 and a pchMOS formed of each electrode of S (source) 71, G (gate) 72, D (drain) 73 and V _DD (power supply voltage) 74. Further, the DMOS is formed from electrodes of S (source) 51 and G (gate) 52 on the first silicon semiconductor substrate 1 side and D (drain) 53 on the second silicon semiconductor substrate 2 side. In addition, doped polysilicon 2
An electrode 80 is formed at 0, and the doped polysilicon 20 becomes an electrical shield layer by connecting the electrode 80 to a fixed potential such as GND or a power supply voltage. In addition, a bipolar transistor and an IGBT (Insulated Gate Bipolar Transistor) are provided in the SOI region 10 and other regions, respectively.
sistor) can also be formed.

The semiconductor device 100 of this embodiment is formed through the following steps. First, as shown in FIG. 2A, an oxide film 11 was formed by thermal oxidation on the main surface (mirror surface side) of the first silicon semiconductor substrate 1 whose one surface was mirror-polished. As the first silicon semiconductor substrate 1, an n ⁻ type substrate having a specific resistance of 0.3 to 10 Ω · cm was used. Next, the resist was patterned by a lithography process, and the oxide film 11 was selectively etched by chemical etching or reactive ion etching. Then, as shown in FIG. 2 (b), the remaining silicon oxide film 11 is used as a mask to separate the first silicon semiconductor substrate 1 from the second silicon semiconductor substrate 2 by chemical etching or reactive ion etching. The recess 5 was formed. The depth of the recess 5 was 0.5 to 3 μm. (First Step) Next, as shown in FIG. 2C, a groove 6 for element isolation was formed in the recess 5 by the same method as in FIG. 2B. The depth of the groove 6 was 0.1 to 10 μm from the recess 5, and the width of the groove 6 was 0.5 to 20 μm. (First Step) Next, as shown in FIG. 2D, a first oxide film 12 which is an isolation thermal oxide film is formed on the entire main surface side of the first silicon semiconductor substrate 1, and the first oxide film 12 is formed. Doped polysilicon 20 was formed on top. (Second step)

Then, as shown in FIG. 3E, the doped polysilicon 20 and the first oxide film 12 are left only in the recess 5 and the groove 6 by patterning. Next, FIG.
As shown in (f), the second silicon semiconductor substrate 2 whose one surface is mirror-polished is used, and the main surface side (mirror surface side) of the first silicon semiconductor substrate 1 and the second silicon semiconductor substrate 2 are used. The mirror surface side of was joined. (Third Step) Then, the bonded first silicon semiconductor substrate 1 and second
A cavity 8 is formed between the cavity 8 and the silicon semiconductor substrate 2. The cavity 8 is secured as a passage (introduction groove) for oxygen in a later step by widening the width of the groove 6 with respect to the film thickness of the first oxide film 12 and the doped polysilicon 20. Next, as shown in FIG. 3 (g), the doped polysilicon 20 and the mirror surface side of the second silicon semiconductor substrate 2 are thermally oxidized to fill the cavity 8 with an oxide film and separate the thermal oxide film. The second oxide film 14 is formed.
(Third Step) Then, the SOI region 10 is made to have a desired thickness by grinding and polishing from the side opposite to the main surface of the first silicon semiconductor substrate 1. The depth of the recess 5 is designed so that the recess 5 is filled with the thermal oxidation of the first silicon semiconductor substrate 1 and the thermal oxidation of the second silicon semiconductor substrate 2 and the doped polysilicon 20. At this time, the thickness of the doped polysilicon 20 is designed so that the doped polysilicon is not lost by the thermal oxidation.

The first formed through the steps as described above
After finishing the grinding and polishing of the side opposite to the main surface of the silicon semiconductor substrate 1, a desired transistor was formed in that portion, and the semiconductor device 100 having the circuit configuration as shown in FIG. 1 could be obtained. The semiconductor device 100 includes the doped polysilicon 20.
By utilizing the thermal oxidation of the double first and second oxide films 12,
Since No. 14 was formed, the oxide film around the SOI region 10 was thick, and the thermal mutual interference between the elements could be reduced. Further, the doped polysilicon 20 layer sandwiched between the first and second oxide films 12 and 14 is grounded by using the electrode 80.
Alternatively, by connecting to a fixed potential such as a power supply voltage, the doped polysilicon 20 layer serves as an electrical shield layer for the first and second silicon semiconductor substrates 1 and 2 and adjacent elements, and electrical mutual interference between the elements is reduced. did it.

Further, using the method for manufacturing a semiconductor device of the present invention, for example, between the step of FIG. 2 (c) and the step of FIG. 2 (d), the impurity layer is formed on the main surface side of the silicon semiconductor substrate 1. Can be formed. Then, the buried diffusion layer 30 as shown in FIG. 4 can be formed around the SOI region, and the diffusion layer 30 can also be used as an electrical shield layer.

[Brief description of drawings]

FIG. 1 is a schematic view showing a structure of an SOI region formed by using a method for manufacturing a semiconductor device according to a specific example of the present invention.

FIG. 2 is a schematic view showing a process sequence of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 3 is a schematic diagram following FIG. 2 showing a process sequence of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 4 is a schematic view showing the structure of another SOI region formed by using the method for manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

 1-First Silicon Semiconductor Substrate 2-Second Silicon Semiconductor Substrate 5-Recess 6-Groove 8-Cavity 10-SOI Region 12-First Oxide Film 14-Second Oxide Film 20-Doped Polysilicon

Claims (1)

[Claims] 1. A first step of forming a groove portion for element isolation and a recess portion for separating the second silicon semiconductor substrate on the mirror surface side of the first silicon semiconductor substrate, and a heat treatment for the groove portion and the recess portion. A second step of sequentially forming a first oxide film and doped polysilicon by oxidation, and a mirror surface side of the first silicon semiconductor substrate and a mirror surface side of the second silicon semiconductor substrate are joined together to form the groove portion. And a third step of forming a second oxide film by thermally oxidizing the concave portion again and at least filling the concave portion with the second oxide film.