JP2000068473A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be formed readily in few number of processes and is superior in frequency characteristics, and a manufacturing method thereof. SOLUTION: An MOS capacitor 10 and a PMOS transistor 20 are formed on a substrate 1. In addition to a lower electrode 12, a dielectric film 13, an upper electrode and an electrode extraction region 15, a voltage impressing region 17 whose conductivity type is different from that of the lower electrode 12 is provided in the MOS capacitor 10. Charges can be forcibly injected into the lower electrode 12 by impress a forward voltage between the voltage impressing region 17 and the electrode extraction region 15, thus reducing the resistance. The voltage impressing region 17 is formed in the same process as a source region 25a and a drain 27a of the PMOS transistor 20. Therefore, frequency characteristics can be improved without increasing the number of processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitor and a method of manufacturing the same.
The present invention relates to a semiconductor device having a (Metal-Oxide-Semiconductor) type capacitor or a MIS (Metal-Insulator-Semiconductor) type capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the display market has been rapidly expanding with the increase in size of personal computers and home televisions. In such a display field, CRT (cathode ray) is currently used because of its excellent visibility such as high definition, high brightness, wide viewing angle and high contrast.
tube) displays are most commonly used. However, the CRT display has a drawback that an occupied area increases with an increase in size. So CR
As a next-generation display replacing the T display, a flat panel display that can be made thinner and occupies a smaller area, such as a liquid crystal display, a projector display, or a plasma display using a new method using plasma, is expected. Recently, high-definition flat panel displays compatible with high definition have already appeared.

As a result, in the field of semiconductors, ICs that can withstand high voltages of several hundred volts for controlling plasma and have excellent frequency characteristics even at high frequencies.
(Integrated circuit) is required. Therefore, in the field of semiconductors, high breakdown voltage MO
The development of S or high withstand voltage BiCMOS is actively performed.

By the way, such MOS or Bi
When a capacitor is mounted in a CMOS, a gate insulating film of a MOS transistor and a dielectric film of a MOS capacitor may be formed in the same step in order to reduce the number of steps. For example, as shown in FIG. 7, when the MOS capacitor 110 and the high-breakdown-voltage PMOS transistor 120 are formed on the same substrate 101, the MOS capacitor 1
10 can be entirely formed by the same process as the PMOS transistor 120 without increasing other processes.

That is, first, n-type semiconductor layers 111 and 121 are epitaxially grown on a substrate 101 made of a p-type semiconductor.
The mold well region 122 and the lower electrode 112 of the MOS capacitor 110 are formed by the same process. Next, after forming interlayer insulating films 119a and 129a, P
The gate insulating film 123 of the MOS transistor 120 and the MO
The dielectric film 113 of the S capacitor 110 is formed by the same process. Subsequently, the PMOS transistor 1
The 20 gate electrodes 124 and the upper electrode 114 of the MOS capacitor 110 are formed by the same process. Further, the potential extraction region 1 of the PMOS transistor 120
25b and an electrode extraction region 115 for the lower electrode 112 of the MOS capacitor 110 are formed by the same process. Thus, the MOS capacitor 110
Can be formed.

[0006]

However, when the MOS capacitor 110 is formed in this manner, the
Since the lower electrode 112 of the S capacitor 110 is formed in the same process as the first conductivity type well region 122 of the PMOS transistor 120, the impurity concentration is 1 × 10 ¹⁶ cm ^−3.
It will be low. Since the frequency characteristic of the MOS capacitor 110 is proportional to the reciprocal of the parasitic resistance of the lower electrode 112, the lower the impurity concentration of the lower electrode 112, the more the frequency characteristic of the MOS capacitor 110 deteriorates. Therefore, in order to improve the frequency characteristics, it is necessary to increase the impurity concentration of the lower electrode 112. However, the dielectric film 113 is formed by the same process as the gate insulating film 123 of the PMOS transistor 120, and the upper electrode 114 is formed by the PMOS. Since the gate electrode 124 is formed in the same step as the gate electrode 124 of the transistor 120, a high-concentration impurity layer such as the potential extraction region 125 b of the PMOS transistor 120 cannot be introduced to the surface of the lower electrode 112.

That is, unless another process is added to the manufacturing process of the PMOS transistor 120, the lower electrode 112
It is not possible to introduce an impurity layer having a high impurity concentration of about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ into the MOS transistor 110 having excellent frequency characteristics in the same process as the PMOS transistor 120. Could not. Therefore, the conventional MOS capacitor has a problem that a capacitor having excellent frequency characteristics cannot be easily obtained with a small number of steps.

In the prior art relating to a MOS capacitor, an upper electrode is formed via a dielectric film on a first conductivity type impurity layer serving as a lower electrode, and the upper electrode is sandwiched in a region of the lower electrode. A pair of second conductivity type impurity layers is formed, and a voltage application electrode different from the upper electrode is provided on the second conductivity type impurity layer via a dielectric film (Japanese Patent Application Laid-Open No. 59-175157). No.). This MO
The S capacitor accumulates electric charges on the surface of the first conductivity type impurity layer by applying a voltage to the voltage application electrode. However, in this MOS capacitor, only a potential corresponding to the built-in potential can be generated, and the potential cannot be arbitrarily selected. That is,
It is not possible to generate a potential difference large enough to improve the frequency characteristics.

Further, as another prior art, a first conductivity type impurity layer serving as a lower electrode is formed in a second conductivity type semiconductor layer, and an electrode is provided for the second conductivity type semiconductor layer. There is also a device in which a reverse voltage is applied between the conductivity type impurity layer and the second conductivity type semiconductor layer (Japanese Patent Laid-Open No. 3-155).
No. 659). However, in this MOS capacitor,
Since a reverse voltage is applied between the first conductivity type impurity layer and the second conductivity type semiconductor layer, carriers cannot be collected on the surface of the first conductivity type impurity layer, and the frequency characteristics cannot be improved. Can not.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device which can be easily formed with a small number of steps and has excellent frequency characteristics, and a method of manufacturing the same. It is in.

[0011]

A semiconductor device according to the present invention comprises a first electrode made of a semiconductor of a first conductivity type provided in a first region, and a first region adjacent to the first electrode. A second electrode provided in the first region so as to face the first electrode through the dielectric film, and a first conductive film provided in the first region. An electrode extraction region for extracting a first electrode made of a mold semiconductor; an extraction electrode for extracting a first electrode provided in the first region adjacent to the electrode extraction region; A voltage application region formed of the second conductivity type semiconductor provided, and a voltage application electrode provided in the first region adjacent to the voltage application region, between the electrode extraction region and the voltage application region. Is applied with a forward voltage.

In another semiconductor device according to the present invention, a first electrode made of a first conductivity type semiconductor provided in a first region, and a first electrode provided in the first region adjacent to the first electrode. A dielectric film, a second electrode provided in the first region so as to face the first electrode via the dielectric film, and a first conductive type semiconductor provided in the first region. First
An electrode extraction region for extracting the first electrode, an extraction electrode for extracting the first electrode provided in the first region adjacent to the electrode extraction region, and an extraction electrode provided in the first electrode region. The semiconductor device includes a voltage application region made of a second conductivity type semiconductor and a voltage application electrode provided in the first region adjacent to the voltage application region.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first electrode made of a semiconductor of a first conductivity type in a first region and a step of forming a dielectric in the first region adjacent to the first electrode are performed. Forming a film, forming a second electrode in the first region so as to face the first electrode via the dielectric film, and forming an electrode made of the first conductivity type semiconductor in the first region. Forming an extraction region, forming an extraction electrode in the first region adjacent to the electrode extraction region, and forming a voltage application region made of the second conductivity type semiconductor in the region of the first electrode And forming a voltage application electrode in the first region adjacent to the voltage application region.

According to another method of manufacturing a semiconductor device according to the present invention, a first electrode made of a semiconductor of a first conductivity type is formed in a first region and electrically separated from the first region by the same process. Forming a first conductive type well region in the formed second region, forming a dielectric film adjacent to the first electrode in the first region, and forming a second conductive film in the second region by the same process. A second electrode is formed in the first region so as to face the first electrode through the dielectric film by the same process as forming the gate insulating film adjacent to the one conductivity type well region; Forming a gate electrode in the second region so as to face the first conductivity type well region with the gate insulating film interposed therebetween, and forming an electrode extraction region made of the first conductivity type semiconductor in the first region by the same process. Is formed, and a voltage is formed in the well region of the first conductivity type. Forming an extraction area,
The step of forming an extraction electrode adjacent to the electrode extraction area in the first area is the same as the step of forming the extraction electrode in the first area.
While forming a voltage application region made of a conductive semiconductor,
The method includes a step of forming a source region and a drain region in the second region so as to sandwich the gate electrode, and a step of forming a voltage application electrode in the first region adjacent to the voltage application region.

In the semiconductor device according to the present invention, when a voltage is applied between the first electrode and the second electrode, electric charges are accumulated at the interface between the first electrode and the dielectric film. At this time, a forward voltage is applied between the electrode extraction region and the voltage application region. Thereby, charge is forcibly injected into the first electrode, and the resistance in the first electrode is reduced.

In another semiconductor device according to the present invention, when a voltage is applied between the first electrode and the second electrode, charges are accumulated at the interface between the first electrode and the dielectric film. Here, since the electrode extraction region is provided with a voltage application region made of a second conductivity type semiconductor having a different conductivity type, by applying a forward voltage between the electrode extraction region and the voltage application region, Charge is forcibly injected into the first electrode. Therefore, the resistance in the first electrode is reduced.

In the method of manufacturing a semiconductor device according to the present invention,
In the first region, first, a first electrode made of a first conductivity type semiconductor is formed. Next, a dielectric film is formed adjacent to the first electrode. Subsequently, a second electrode is formed so as to face the first electrode via the dielectric film. Further, an electrode extraction region made of the first conductivity type semiconductor is formed, and an extraction electrode is formed adjacent to the electrode extraction region. Further, a voltage application region made of the second conductivity type semiconductor is formed in the region of the first electrode, and the voltage application electrode is formed adjacent to the voltage application region.

In another method of manufacturing a semiconductor device according to the present invention, first, a first electrode made of a first conductivity type semiconductor is formed in a first region, and a second electrode is formed in the same step as the first electrode.
In the region, the first conductivity type well region is formed. Next, a dielectric film is formed in the first region adjacent to the first electrode, and a gate insulating film is formed in the second region adjacent to the first conductivity type well region by the same process. . Subsequently, a second electrode is formed in the first region so as to face the first electrode via the dielectric film,
By the same process, a gate electrode is formed in the second region so as to face the first conductivity type well region via the gate insulating film. In the first region, an electrode extraction region made of the first conductivity type semiconductor is formed, and by the same process as this, a potential extraction region is formed in the first conductivity type well region. After that, an extraction electrode is formed in the first region adjacent to the electrode extraction region. Further, a voltage application region made of the second conductivity type semiconductor is formed in the first region, and a source region and a drain region are formed in the second region so as to sandwich the gate electrode by the same process. After that, a voltage application electrode is formed in the first region adjacent to the voltage application region.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a configuration of a memory which is a semiconductor device according to an embodiment of the present invention. This memory has a first region 1a and a second region 1b on a substrate 1 made of, for example, p-type silicon (Si).
In the first region 1a, a MOS capacitor 1 as a capacitor is provided.
0 is formed, and P as a switch is provided in the second region 1b.
A MOS transistor 20 is formed.

The MOS capacitor 10 is placed on the substrate 1
For example, it has an n-type semiconductor layer 11 made of n-type silicon doped with an n-type impurity such as phosphorus (P). This n
The type semiconductor layer 11 has, for example, a resistivity of 5 to 10 Ω · cm.
The thickness is generally determined to be about 10 μm per 100 V in accordance with the required breakdown voltage. A lower electrode 12 as a first electrode is formed inside the n-type semiconductor layer 11 from the surface of the n-type semiconductor layer 11 toward the substrate 1. The lower electrode 12 is made of, for example, n-type silicon to which an n-type impurity such as phosphorus is added, and has an impurity concentration of 1 × 10 ¹³ to 1 × 10 ^13.
It is about × 10 ¹⁴ cm ^-2 .

On a part of the surface of the lower electrode 12, a dielectric film 13 made of an oxide film is formed adjacent to the lower electrode 12. The thickness of the dielectric film 13 is, for example, 20 to 5
It is about 0 nm. An upper electrode 14 as a second electrode is formed on the dielectric film 13 so as to face the lower electrode 12. The upper electrode 14 has a two-layer structure in which a polysilicon layer 14a made of n-type polysilicon doped with an n-type impurity such as phosphorus and a metal layer 14b made of a metal such as aluminum (Al) are stacked. ing. Of these, the polysilicon layer 14a is the dielectric film 1
It is located on the 3rd side. The thickness of the polysilicon layer 14a is, for example, about 400 nm, and the thickness of the metal layer 14b is, for example, about 400 nm.

In another part of the surface of the lower electrode 12, an electrode extraction region 15 made of n-type silicon doped with an n-type impurity such as arsenic (As) is formed in the region of the lower electrode 12. . The impurity concentration of the electrode extraction region 15 is, for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . An extraction electrode 16 made of a metal such as aluminum is formed on the electrode extraction region 15. The electrode extraction region 15 and the extraction electrode 16 are for extracting the lower electrode 12, and a voltage is applied between the lower electrode 12 and the upper electrode 14 through these.

In still another part of the surface of the lower electrode 12,
In the region of the lower electrode 12, p such as boron (B)
A voltage application region 17 made of p-type silicon doped with a type impurity is formed. The voltage application region 17 is located so as to face the electrode extraction region 15 with the upper electrode 14 interposed therebetween. The impurity concentration of the voltage application region 17 is, for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . A voltage application electrode 18 made of a metal such as aluminum is formed on the voltage application region 17. The voltage application region 17 and the voltage application electrode 18
As shown in FIG. 2, a forward voltage is applied between the lower electrode 12 and the electrode extraction region 15 to forcibly inject electric charges into the lower electrode 12 to lower the resistance. .

The electrode extraction regions 15 and 16 formed on the surface of the lower electrode 12 and between the extraction electrode 16 and the upper electrode 14, the voltage application region 17 and between the voltage application electrode 18 and the upper electrode 14, or Between the region 15 and the extraction electrode 16 and the voltage application region 17 and the voltage application electrode 18, interlayer insulating films 19a and 19b made of oxide films are formed, respectively. For example, the thickness of the interlayer insulating film 19a is 500-70.
The thickness is about 0 nm, and the thickness of the interlayer insulating film 19b is about 600 nm.

The PMOS transistor 20 has an n-type semiconductor layer 21 formed on the substrate 1 in the same step as the n-type semiconductor layer 11 of the MOS capacitor 10. That is, the n-type semiconductor layer 21 has the same configuration as the n-type semiconductor layer 11. n inside the n-type semiconductor layer 21
An n-type well region 22 as a first conductivity type well region is formed from the surface of the type semiconductor layer 21 toward the substrate 1. This n-type well region 22 is
The lower electrode 12 is formed in the same process as the lower electrode 12, and has the same configuration as the lower electrode 12.

A part of the surface of the n-type well region 22 has n
A gate insulating film 23 made of an oxide film is formed adjacent to the mold well region 22. This gate insulating film 23 is made of M
It is formed in the same process as the dielectric film 13 of the OS capacitor 10 and has the same configuration as the dielectric film 13. On the gate insulating film 23, an n-type well region 22 is formed.
A gate electrode 24 is formed so as to face. The gate electrode 24 is formed in the same process as the upper electrode 14 of the MOS capacitor
4 has the same configuration as that of FIG. That is, although the metal layer is not shown in FIG.
a and a metal layer. The metal layer is shown in FIG.
Although it is not formed on the cross section shown in FIG. 1, it is formed on the polysilicon layer in other places.

In another part of the surface of the n-type well region 22, a source region 25a and a potential extraction region 25b are formed adjacent to each other in the region of the n-type well region 22. Of these, the source region 25a is
It is formed in the same step as the voltage application region 17 of the capacitor 10 and has the same configuration as the voltage application region 17. That is, it is made of p-type silicon having a high impurity concentration. Further, the potential extraction region 25b
Are formed in the same process as the electrode extraction region 15 of the MOS capacitor 10, and the electrode extraction region 1
5 has the same configuration as that of FIG. That is, it is made of n-type silicon having a high impurity concentration.

A source electrode 26 is formed on the source region 25a and the potential extraction region 25b. The source electrode 26 is connected to the extraction electrode 16, the voltage application electrode 18, and the upper electrode 14 of the MOS capacitor 10.
Are formed in the same step as the metal layer 14b, and have the same configuration.

In the inside of the n-type semiconductor layer 21, a p-type well region 27 as a second conductivity type well region is formed from the surface of the n-type semiconductor layer 21 toward the substrate 1. The p-type well region 27 is provided adjacent to the n-type well region 22, and is located so as to face the source region 25a and the potential extraction region 25b with the gate insulating film 23 interposed therebetween. The p-type well region 27 is made of p-type silicon to which a p-type impurity such as boron is added, and has an impurity concentration of 1 × 10 ¹³ to 1 × 10 3.
It is about ¹⁴ cm ^-2 .

On the surface of p-type well region 27, a drain region 27a is formed in the region of p-type well region 27. The drain region 27a is formed in the same step as the voltage application region 17 of the MOS capacitor 10, and has the same configuration as the voltage application region 17. That is, the source region 25a is formed in the same step, and is made of p-type silicon having a high impurity concentration similarly to the source region 25a. A drain electrode 28 is formed on the drain region 27a.
The drain electrode 28 is formed in the same step as the metal layer 14b of the extraction electrode 16, the voltage application electrode 18 and the upper electrode 14 of the MOS capacitor 10, and has the same configuration.

The source region 25a, the potential extraction region 25b and the drain region 27 between the source electrode 26 and the gate electrode are formed in the n-type semiconductor layer 21, respectively.
a and the drain electrode 28 and the gate electrode, or between the source region 25a, the potential extraction region 25b and the source electrode 26 and the drain region 27a and the drain electrode 28, an interlayer insulating film 29a, 2 made of an oxide film.
9b are respectively formed. This interlayer insulating film 29a
Are formed in the same step as the interlayer insulating film 19a of the MOS capacitor 10, and the interlayer insulating film 29b is formed in the same step as the interlayer insulating film 19b.

Note that element isolation regions 2 are formed around the first region 1a and around the second region 1b, respectively. This element isolation region is 1 × 10 ¹⁴ to 1 × 10
It is made of silicon to which boron or aluminum is added at a concentration of about ¹⁵ cm ^-2 .

A memory having such a configuration can be manufactured as follows.

3 to 6 show the manufacturing method in the order of each step. First, as shown in FIG.
For example, a CVD (Ch
An n-type silicon layer is epitaxially grown by an emical vapor deposition method. Thereby, the first area 1
a, an n-type semiconductor layer 11 is formed in the second region 1
At b, an n-type semiconductor layer 21 is formed. Next, for example, by steam oxidation at about 900 to 1000 ° C.
The surfaces of these n-type semiconductor layers 11 and 21 are oxidized to form an oxide film 31 having a thickness of about 60 to 100 nm.

Subsequently, as shown in FIG.
Boron or aluminum is selectively implanted around the region 1a and around the second region 1b using, for example, a photolithography technique and an ion implantation technique to form the element isolation region 2. After the element isolation region 2 is formed, the photoresist film (not shown) is removed, and then the region where the lower electrode 12 is formed in the first region 1a and the region where the n-type well region 22 is formed in the second region 1b are formed. For example, an n-type impurity such as phosphorus is selectively implanted by using a photolithography technique and an ion implantation technique. Thereby, the lower electrode 12 is formed in the first region 1a, and the n-type well region 22 is formed in the second region 1b.

After the lower electrode 12 and the n-type well region 22 are formed, the photoresist film (not shown) is removed, and the second electrode is formed as shown in FIG.
A p-type impurity such as boron is selectively implanted into a region of the region 1b where the p-type well region 27 is to be formed by using, for example, a photolithography technique and an ion implantation technique. As a result, a p-type well region 27 is formed in the second region 1b.

After the formation of the p-type well region 27, the photoresist film (not shown) is removed, and then, for example, low pressure CVD is performed on the oxide film 31 as shown in FIG.
Silicon nitride (S) having a thickness of about 80 to 100 nm
i ₃ N ₄ ) Film 32 is formed. After forming the silicon nitride film 32, for example, heat treatment at about 1100 to 1200 ° C. is performed to activate the impurities introduced into the element isolation region 2, the lower electrode 12, the n-type well region 22 and the p-type well region 27, respectively. Let it. After that, photolithography technology and reactive ion etching (Reactive Ion E
The silicon nitride film 32 is selectively removed by using a tching (RIE) method. As a result, in the first region 1a, the formation regions of the dielectric film 13, the electrode extraction region 15, and the voltage application region 17 are covered with the silicon nitride film 32, respectively, and in the second region 1b, the gate insulating film 23 is formed. ,
The respective formation regions of the source region 25a, the potential extraction region 25b, and the drain region 27a are covered with the silicon nitride film 32, respectively.

After the silicon nitride film 32 is selectively removed, a photoresist film (not shown) is removed.
As shown in (B), for example, using the silicon nitride film 32 as a mask, the interlayer insulating film 1 having a thickness of about 500 to 1000 nm is formed by steam oxidation at about 950 to 1000 ° C.
9a and 29a are selectively formed. After forming the interlayer insulating films 19a and 29a, the silicon nitride film 32 is removed by, for example, hot phosphoric acid. Then, for example, using a solution containing hydrogen fluoride,
2. The oxide film 31 on the surface of the n-type well region 22 and the p-type well region 27 is removed.

After the oxide film 31 is removed, as shown in FIG. 5, for example, an oxide film serving as the dielectric film 13 and the gate insulating film 23 is formed by steam oxidation at about 950 to 1000 ° C. After forming an oxide film, for example, C
A semiconductor layer to be the polysilicon layer 14a of the upper electrode 14 and the polysilicon layer 24a of the gate electrode 24 is formed by the VD method. After forming the semiconductor layer, the semiconductor layer and the oxide film are selectively removed by using, for example, a photolithography technique and an RIE method. Thereby, the dielectric film 13 and the upper electrode 14 are formed in the first region 1a.
Polysilicon layers 14a are formed respectively, and a gate insulating film 23 and a gate electrode 24 are formed in the second region 1b.
Are formed respectively. Then, after removing the photoresist film (not shown), for example, steam oxidation at about 800 to 900 ° C.
An oxide film (not shown) having a thickness of about 20 nm is formed.

After forming an oxide film (not shown), as shown in FIG. 6, the electrode extraction region 15 of the first region 1a is formed.
Is formed, and an n-type impurity such as arsenic is selectively implanted into the region where the potential extraction region 25b of the second region 1b is formed by using, for example, photolithography technology and ion implantation technology. Thus, the electrode extraction region 15 is formed in the first region 1a, and the potential extraction region 25 is formed in the second region 1b.
b is formed. After forming the electrode take-out region 15 and the potential take-out region 25b, respectively, the photoresist film (not shown) is removed, and then the region where the voltage application region 17 of the first region 1a is formed and the source region 25a of the second region 1b For example, a p-type impurity such as boron is selectively implanted into a region where the drain region 27a and the drain region 27a are formed by using a photolithography technique and an ion implantation technique. Thus, the voltage application region 17 is formed in the first region 1a, and the source region 25a and the drain region 27a are formed in the second region 1b.

After the voltage application region 17, the source region 25a, and the drain region 27a are formed, the photoresist film (not shown) is removed, and the same process as in FIG.
As shown in (B), the interlayer insulating films 19b and 29b are formed by, for example, the CVD method. After that, for example, a heat treatment at about 850 to 950 ° C. is performed, and the electrode extraction region 15, the voltage application region 17, the source region 25a,
The impurities introduced into the potential extraction region 25b and the drain region 27a are respectively activated.

After the heat treatment, the interlayer insulating film 19 is formed using, for example, photolithography and RIE.
b and 29b are selectively removed. This allows
The electrode extraction region 15, the polysilicon layer 14a and the voltage application region 17 are exposed in the first region 1a, respectively, and the source region 25a, the potential extraction region 25b, the polysilicon layer 24a and the drain region 27a are respectively defined in the second region 1b. Will be exposed. Thereafter, for example, a metal layer is deposited by a vacuum deposition method, and the metal layer formed on the photoresist film (not shown) is removed (lift-off) together with the photoresist film. Thereby, the extraction electrode 16, the metal layer 14b of the upper electrode 14, the voltage application electrode 18, the source electrode 26, the metal layer of the gate electrode 24, and the drain electrode 28 are formed. Thus, the memory shown in FIG. 1 is formed.

Such a memory operates as follows.

In this memory, when writing, P
By changing the voltage applied to the gate electrode 24 of the MOS transistor 20, the PMOS transistor 20 is turned on. As a result, a voltage is applied between the lower electrode 12 and the upper electrode 14 of the MOS capacitor 10, and charges are accumulated at the boundary between the lower electrode 12 and the dielectric film 13. At this time, in the MOS capacitor 10, a forward voltage is also applied between the voltage application region 17 and the electrode extraction region 15. As a result, charges are forcibly injected into the lower electrode 12, and the resistance of the lower electrode 12 decreases.

The charge stored in the MOS capacitor 10 is held by turning off the PMOS transistor 20. At the time of reading, similarly, the PMOS transistor 20 is turned on and the charge stored in the MOS capacitor 10 is detected. During the holding and reading, the voltage application region 17 of the MOS capacitor 10 and the electrode extraction region 1 are also used.
5, a voltage is applied in the forward direction.

As described above, according to the memory of the present embodiment, the MOS capacitor 10 is provided with the voltage application region 17, so that the forward voltage is applied between the voltage application region 17 and the electrode extraction region 15. By applying the charges, charges can be forcibly injected into the lower electrode 12. Therefore, the resistance of the lower electrode 12 can be reduced, and the frequency characteristics can be improved.

The voltage application region 17 is a source region 25a and a drain region 27 of the PMOS transistor 20.
Since it can be formed by the same process as a, it can be easily manufactured with a small number of processes without adding a new process.

Further, according to the method of manufacturing a memory according to the present embodiment, since the voltage application region 17 is formed in the first region, the memory according to the present embodiment can be easily manufactured. Thus, the memory according to the present embodiment can be realized. In addition, since the source region 25a and the drain region 27a of the PMOS transistor 20 are formed in the same step, the number of steps can be reduced.

The present invention has been described with reference to the embodiments. However, the present invention is not limited to these embodiments, and can be variously modified. For example, in the above embodiment, the voltage application region 17 is replaced with the electrode extraction region 15.
Although it is formed at a position opposite to the above, it may be formed at another position. For example, it may be formed in a U shape so as to surround the dielectric film 13. Further, in the above-described embodiment, the voltage application region 17 is formed on the surface of the lower electrode 12, but may be formed inside the lower electrode or on the substrate 1 side.

Further, in the above embodiment, the metal layer 14b of the upper electrode 14, the extraction electrode 16, the voltage application electrode 18, the metal layer of the gate electrode 24, the source electrode 26 and the drain electrode 28 are made of metal such as aluminum. However, it can be made of another metal. Further, a laminated structure including a plurality of layers may be provided. For example, a structure having a titanium layer, a compound layer made of a compound of titanium, oxygen and nitrogen, a barrier metal layer in which a titanium layer and an aluminum layer are sequentially laminated may be used.

In addition, in the above-described embodiment, the lower electrode 12 and the electrode lead-out region 15 are each formed of an n-type semiconductor, and the voltage application region 17 is formed of a p-type semiconductor. The electrode extraction region 15 may be formed of a p-type semiconductor, and the voltage application region 17 may be formed of an n-type semiconductor.

Further, in the above embodiment, M
Although the memory including the OS capacitor 10 and the PMOS transistor 20 has been described, the present invention can be widely applied to other semiconductor devices. For example, M
A semiconductor device such as a memory including an OS capacitor and an NMOS transistor, or a MIS capacitor and a MI device
The present invention can be applied to a semiconductor device having an S transistor and the like.

[0054]

As described above, according to the semiconductor device of the first or second aspect, the first electrode and the electrode take-out region are provided with a voltage application region having a different conductivity type from the voltage application region and the electrode take-out region. Since a forward voltage is applied to the region, electric charge can be forcibly injected into the first electrode, and the resistance of the first electrode can be reduced. Therefore, there is an effect that the frequency characteristics can be improved.

In particular, according to the semiconductor device of the present invention, since the source region and the drain region formed in the same step as the voltage application region are provided, the number of steps can be reduced without adding a new step. There is an effect that it can be easily manufactured.

According to the semiconductor device of any one of claims 3 to 5, the voltage application region formed in the region of the first electrode and having a different conductivity type from the first electrode and the electrode extraction region is formed. With this configuration, by applying a forward voltage between the voltage application region and the electrode extraction region, charges can be forcibly injected into the first electrode. Therefore, the resistance of the first electrode can be reduced,
There is an effect that the frequency characteristics can be improved.

In particular, according to the semiconductor device of the fifth aspect, since the source region and the drain region formed by the same process as the voltage application region are provided, the same effect as that of the semiconductor device of the second aspect is obtained. Play.

Further, according to the method of manufacturing a semiconductor device according to the sixth or seventh aspect, the voltage application region is formed, so that the semiconductor device of the present invention can be easily manufactured. There is an effect that a semiconductor device can be realized.

In addition, according to the method of manufacturing a semiconductor device according to the seventh or eighth aspect, the voltage application region is formed in the same step as the source region and the drain region in the second region. This eliminates the need for additional steps, thereby reducing the number of steps.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating the semiconductor device shown in FIG. 1;

3 is a cross-sectional view illustrating each manufacturing process of the semiconductor device illustrated in FIG.

FIG. 4 is a sectional view illustrating each manufacturing step following FIG. 3;

FIG. 5 is a sectional view illustrating each manufacturing step following FIG. 4;

FIG. 6 is a sectional view illustrating each manufacturing step following FIG. 5;

FIG. 7 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

[Explanation of symbols]

1, 101: substrate, 1a: first region, 1b: second region, 2: element isolation region, 10, 110: MOS capacitor, 11, 21, 111, 121: n-type semiconductor layer, 1
2, 112 ... lower electrode (first electrode), 13, 113 ...
Dielectric film, 14, 114 ... upper electrode (second electrode), 1
4a, 24a: polysilicon layer, 14b: metal layer, 1
5,115 ... electrode extraction region, 16 ... extraction electrode,
17: voltage application area, 18: voltage application electrode, 19a, 1
9b, 29a, 29b, 119a, 129a ... interlayer insulating films, 20, 120 ... PMOS transistors, 22, 12
2 ... n-type well region, 23, 123 ... gate insulating film, 2
4, 124 gate electrode, 25a source region, 25
b, 125b: potential extraction region, 26: source electrode,
27 ... p-type well region, 27a ... drain region, 28 ...
Drain electrode, 31: oxide film, 32: silicon nitride film

Claims (8)

[Claims] A first electrode made of a first conductivity type semiconductor provided in a first region; a dielectric film provided in the first region adjacent to the first electrode; A second electrode provided in the first region so as to face the first electrode via the body film, and a first electrode provided in the first region and made of a first conductivity type semiconductor. An electrode extraction region for extracting, an extraction electrode for extracting the first electrode provided in the first region adjacent to the electrode extraction region, and a second conductivity type semiconductor provided in the first region And a voltage application electrode provided in a first region adjacent to the voltage application region, and a forward voltage is applied between the electrode extraction region and the voltage application region. A semiconductor device to which voltage is applied. 2. A first conductivity type well region provided in a second region electrically separated from the first region and formed in the same step as the first electrode; A gate insulating film provided in the second region adjacent to the conductive type well region and formed in the same step as the dielectric film; and facing the first conductive type well region via the gate insulating film. A gate electrode provided in the second region and formed in the same step as the second electrode; and a potential extraction provided in the first conductivity type well region and formed in the same step as the electrode extraction region. 2. The semiconductor device according to claim 1, further comprising: a region; and a source region and a drain region provided in the second region so as to sandwich the gate electrode therebetween and formed by the same process as the voltage application region. Semiconductor device 3. A first electrode made of a first conductivity type semiconductor provided in a first region; a dielectric film provided in the first region adjacent to the first electrode; A second electrode provided in the first region so as to face the first electrode via the body film, and a first electrode provided in the first region and made of a first conductivity type semiconductor. An electrode extraction region for extracting, an extraction electrode for extracting the first electrode provided in the first region adjacent to the electrode extraction region, and a second electrode provided in the region of the first electrode. A semiconductor device comprising: a voltage application region made of a two-conductivity type semiconductor; and a voltage application electrode provided in a first region adjacent to the voltage application region. 4. The semiconductor device according to claim 3, wherein a forward voltage is applied between said electrode extraction region and said voltage application region. 5. A first conductivity type well region provided in a second region electrically separated from the first region and formed in the same step as the first electrode; A gate insulating film provided in the second region adjacent to the conductive type well region and formed in the same step as the dielectric film; and facing the first conductive type well region via the gate insulating film. A gate electrode provided in the second region and formed in the same step as the second electrode; and a potential extraction provided in the first conductivity type well region and formed in the same step as the electrode extraction region. 4. The semiconductor device according to claim 3, further comprising: a region, a source region and a drain region provided in the second region so as to sandwich the gate electrode therebetween, and formed by the same process as the voltage application region. Semiconductor device 6. A step of forming a first electrode made of a first conductivity type semiconductor in a first region; a step of forming a dielectric film adjacent to the first electrode in the first region; A step of forming a second electrode in the first area so as to face the first electrode via the dielectric film, a step of forming an electrode extraction area made of the first conductivity type semiconductor in the first area, A step of forming an extraction electrode adjacent to the electrode extraction region in the first region; a step of forming a voltage application region made of the second conductivity type semiconductor in the region of the first electrode; Forming a voltage application electrode adjacent to the application region. 7. A step of forming a first conductivity type well region in a second region electrically separated from the first region by the same process as that of the first electrode; Forming a gate insulating film in the second region adjacent to the first conductivity type well region, and forming the first conductive film in the second region via the gate insulating film in the same step as the second electrode. Forming a gate electrode so as to face the mold well region, forming a potential extraction region in the first conductivity type well region by the same process as the electrode extraction region, and forming a gate electrode in the same step as the voltage application region. 7. The method according to claim 6, further comprising the step of forming a source region and a drain region so as to sandwich the gate electrode in the second region. 8. A first electrode made of a semiconductor of a first conductivity type is formed in a first region by the same process, and a first electrode is formed in a second region electrically separated from the first region. Forming a dielectric film adjacent to the first electrode in the first region and forming a gate adjacent to the first conductivity type well region in the second region by the same step as forming the mold well region. In the same step as the step of forming the insulating film, the second electrode is formed in the first region so as to face the first electrode via the dielectric film, and the gate insulating film is formed in the second region. Forming a gate electrode so as to face the first conductivity type well region through the first conductive type well region, and forming an electrode extraction region made of the first conductivity type semiconductor in the first region and forming the first conductivity type well by the same process. Forming a potential extraction region in the region; Forming a take-out electrode adjacent to the electrode take-out region in the region, forming a voltage application region made of the second conductivity type semiconductor in the first region and sandwiching the gate electrode in the second region by the same process. Forming a source region and a drain region as described above; and forming a voltage application electrode in the first region adjacent to the voltage application region.