JPS62254458A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of a parasitic channel caused by an electric interference by a method wherein a buried channel type is used on the MOSFET of the active layer of two or more layers of the semiconductor device on which a plurality of layers of semiconductor region having an active layer are formed. CONSTITUTION:A buried channel type is used on the active layer of the second layer and above of the MOSFET, and the conductivity types of the MOSFET located at the positions corresponding to the upper and the lower active layers are made opposite to each other. When the lower gate electrode 106 gives an effect upon the lower part of the P-region 114 of the upper MOSFET W1 in the state wherein the MOSFET W1 is laminated, an inversion layer 118 is induced. As electrons are present on the inversion layer 118, it is not turned into the parasitic channel of the FET W1. A buried channel type MOSFET W2 is constituted corresponding to an MOSFET V2 on an insulating film 105. If said FET W2 is a single unit, a neutral region 124 is formed when positive voltage is applied to a gate electrode 123, and it is turned into a buried channel for electrons. When the lower gate electrode 101 gives an effect on the lower part of the N-region 121 of the upper FET W2 in the state wherein the FET W2 is laminated, an inversion layer is induced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which a multilayer semiconductor region having an active layer is formed, and in which there are upper and lower active layers.

Conventional technology In multilayer integrated circuits, the semiconductor regions in which circuit elements are constructed are made thinner than in the past, so the circuit elements in the upper active layer and the circuit elements or wiring in the lower active layer are mounted using conventional mounting methods. are placed an order of magnitude closer to each other than the Therefore, the circuit elements in the upper active layer may receive electrical interference from the electrodes and wiring of the circuit elements in the lower active layer, resulting in malfunction.

FIG. 3 shows a basic integrated circuit that utilizes surface channels in both the first and second layers. FIG. 3 (4) Source n region 302 and drain n region 30
3 is formed, and an insulating film 3o4 is formed.

A gate electrode 306 is formed inside to form one MOSFET.
Further, a thin film-like single crystal is formed on the insulating film 304, and is divided into a source n region 306, a drain n region 3o7, and a p region 308 including a channel.
Then, gel lt T I It is formed through the insulating film 309 .

When a positive voltage is applied to the gate electrode 306 of MO3FΣTtQ Q 1'', an inversion layer 311 is formed and becomes a surface channel.

On the other hand, as shown in Figure 3(t)),
If the MOSFET 305 is a single substance, an inversion layer 312 is formed when a positive voltage is applied to the gate electrode 310, but if it is stacked as shown in FIG. (7) The P region 308 may be affected and a new inversion layer 313 may be induced.

As a result, MO8FK T1'' is controlled not only by the original gate electrode 310 but also by the gate electrode 305 of another MO5FXτ'Q1'', causing malfunction.

FIG. 4 shows a basic integrated circuit utilizing surface channels in the first layer and buried channels in the second layer.

In FIG. 4 (IL), parts common to those in FIG. 3 (TaJ) are given the same numbers. In FIG. , the source n
A region 401, a drain n region 402, an n region 403 including a channel, and a gate electrode 40 via an insulating film 404.
5 is formed, resulting in MO8FXT゛9Q2''. As shown in FIG. It becomes a buried channel, but the fourth
Figure (11J) When stacked, the lower gate electrode 3
05 influences the upper MO8FXT°°T2" drift region 403 and induces a new accumulation layer 4o end and neutral region 408. As a result, MOSFET"
In addition to the original gate electrode 406, T2''
It is also controlled by the gate electrode 306 of T"Ql" and causes malfunction.

Problems to be Solved by the Invention As is clear from the above explanation, one of the problems that must be solved to realize a stacked integrated circuit is the problem of parasitics other than the original channel caused by electrical interference between the upper and lower active layers. One example of this is that a channel is formed, leading to malfunction of the active element.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor device that can prevent the generation of parasitic channels due to electrical interference.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses a buried channel type MO5FIET for the active elements arranged in each active layer (for the 122nd and higher active layers). 2) MO5FIEs in corresponding positions in the upper and lower active layers
The conductivity type of T is reversed, and G3) If the MOSFET in the first active layer is a buried channel type, the above (-) condition is extended and applied from the first layer, and if it is a surface channel type, the corresponding second layer MOSFET is applied. MO of
The region including the SFET and the channel is of the same conductivity type, and the carriers contributing to conduction are of opposite conductivity type.

According to the above-described structure, only the inversion layer is formed even if it is affected by electrical interference between the upper and lower active layers, and a parasitic channel is formed because it becomes a multi-layer that is used in the main operating state of the active element. This will not cause any malfunction.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1o1 is a P-type silicon semiconductor substrate (hereinafter referred to as P substrate), and P substrate 1o1
An n-well region 102 is formed therein.

A surface channel type MO5FXT is formed by a gate electrode 106 provided on the surface of the P substrate 101 via a source n region 103, a drain n region 104, and an insulating film 105.
“v1” is configured. When a positive voltage is applied to the gate electrode 106, an inversion layer 107 is formed and serves as a surface channel for electrons.

On the other hand, the P+ region 1 of the source on the surface of the n-well region 102
0B, drain P region 109, and position 4-L a
The surface channel type MOSFET "V2" is constructed from t a^C as well as the person 1 I Kaiwa ↓ input W. -A^1r.

When a negative voltage is applied to the gate electrode 11o, the inversion layer 11
1 is formed and serves as a surface channel for holes.

MO8FI on 10g of insulation film! A thin film-like single crystal region is formed corresponding to T"Vl", and a P+ region 112 of the source is formed.
, a drain P+ region 113, a P region 114 having a channel, and a gate electrode 116 provided through an insulating film 116 constitute a buried channel type MO8FRT "Wl". If MOSFET "Wl" is a single unit, when a negative voltage is applied to the gate electrode 116, the neutral region 117
is formed and serves as a buried channel for holes. (At this time, even if the neutral region 117 is not formed and is completely empty, the position corresponding to the neutral region 117 has the lowest potential and can still be used as a channel. In that case, MO
SFET "Wl" becomes MOS-8IT. ) However, since the MOSFET "Wl" is in a stacked state, the lower gate electrode 106 is connected to the upper MOSFET "W1".
affecting the bottom of the P region 114 of the inversion layer 118
can induce However, since electrons exist in the inversion layer 118, it does not become a parasitic channel of MOSFET "Wl".

Similarly, on the insulating film 105, a thin film-like single crystal region is formed corresponding to MOSFET "V2", and includes a source n+ region 119, a drain n region 120, an n region 121 having a channel, and an insulating film 122. A buried channel type MO3FXT"" is formed by the gate electrode 123 provided through the
W2'' is configured.

If MOSFET “W2” is a single unit, the gate electrode 123
A neutral region 124 is formed when a positive voltage is applied to
Provides a buried channel for electrons.

(At this time, even if the neutral region 124 is not formed and it becomes completely empty, it will become MOS-8IT as in the case of MOS F RT "W 1 " O, so there will be no operational problem.) , MO8FRT''t W 21' are in a stacked state, so when the lower gate electrode 11o affects the lower part of the n region 121 of the upper MO5FXT layer W2'', an inversion layer 126 can be induced. However, since holes exist in the inversion layer 126, it does not become a parasitic channel of MOSFET "W2".

As described above, according to this embodiment, the MO of the first active layer
The SFET is a surface channel type, and the second active layer is a MOS
The FET is of the buried channel type, and the regions containing the channels of the upper and lower corresponding MO5FK are of the same conductivity type,
Since the majority carriers are of opposite conductivity type, a parasitic channel is not formed even if there is electrical interference between the upper and lower active layers, and malfunctions do not occur.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the invention.

In FIG. 2, a P substrate 201 and an n formed on its surface are shown.
There is a well region 202, a source n+ region 203 on the surface of the P substrate 201, a drain n+ region 204, a buried channel n region 205, and a gate electrode provided via an insulating film 206, t) MO8F. “Yi T”
When a positive voltage is applied to the gate electrode 207, a neutral region 208 is formed and becomes a buried channel for electrons.

A second thin film-like single crystal region is formed on the insulating film 206, and the source P
The MO8FXT"Y1" is constituted by the + region 209, the P+ region 210 for the drain, the P region 211 for the buried channel, and the gate electrode 213 provided through the insulating film 212. When a negative voltage is applied to the gate electrode 213, a neutral region 214 is formed and becomes a buried channel for holes.

Even if the inversion layer 216 is formed due to electrical interference from the lower gate electrode 207, the MO
3FIET"!1" parasitic channel.

It is not.

Similarly, a third thin film-like single crystal region is formed on the insulating film 212, corresponding to MOSFET "τ1", an n region 216 for the source, an n region 217 for the drain, and an n region 218 for the buried channel. , and the gate electrode 220 provided through the insulating film 219, the MOSFET "zl"
is configured. When a positive voltage is applied to the gate electrode 220, a neutral region 221 is formed and serves as a buried channel for electrons.

Even if the inversion layer 222 is formed due to electrical interference from the lower gate electrode 213, the MO8
It does not become a parasitic channel of FKτ゛z1''.

On the other hand, the source P+ region 22 on the surface of the n-well region 202
3. P+ region 224 of drain, P for buried channel
The region 226 and the gate electrode 226 provided through the insulating film 2015 constitute a MO5FIET°°x2''. When a negative voltage is applied to the gate electrode 226, a neutral region 227 is formed, and serves as a buried channel for holes. Become.

In the second thin film-like single crystal region on the insulating film 206, M
O8F] Corresponding to ET "X2", source n+ area 2
28, MOSFET ``!2'' 7 by the drain n region 229, the buried channel n region 23o1, and the gate electrode 231 provided through the insulating film 212.
5: Constructed. When a positive voltage is applied to the gate electrode 231, a neutral region 232 is formed and serves as a buried channel for electrons.

Even if the inversion layer 233 is formed due to electrical interference from the lower gate electrode 226, the MOS
It does not become a parasitic channel of FET "Y2".

Similarly, in the third thin film single crystal region on the insulating film 212, the source P
The MO5FIE! “Z2” is configured. When a negative voltage is applied to the gate electrode 238, a neutral region 239 is formed and serves as a buried channel for holes.

Even if the inversion layer 240 is formed due to electrical interference from the lower gate electrode 231, the presence of electrons
It does not become a parasitic channel of FIT "Z2". In the above explanation, the neutral region 208, 214° 221.227.232
．． Even if 239 does not occur and becomes completely empty, this part becomes the lowest potential region, so the state of the buried channel is maintained.

As described above, according to this embodiment, the MO8FIE of each active layer
All of the MOSFETs are of the buried channel type, and the regions containing the channels of the upper and lower corresponding MOSFETs are of opposite conductivity type, and the majority carriers are also of opposite conductivity type, so that even if there is electrical interference between the upper and lower active layers, No parasitic channels are formed;
No malfunction will occur. Furthermore, according to this embodiment, a buried channel type CMO3FIET can be realized without worrying about electrical interference by reversing the conductivity types of the upper and lower active layers.

Furthermore, the buried channel does not utilize the interface with poor crystallinity of the thin film-like single crystal region, which helps improve the performance of the MOSFET.

Note that in this embodiment, the region for the buried channel may be a near-intrinsic (including, of course, intrinsic) region containing almost no impurities.

Effects of the Invention As described above, according to the present invention, the MOSFET of the upper and lower active layers
Even if electrical interference occurs, it is possible to prevent the generation of parasitic channels caused by minority carrier inversion layer interference, which has great practical value.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, and FIGS. 3 and 4 are conventional semiconductor devices. FIG. 101...P-type silicon semiconductor substrate, Vl, V
2...1 surface channel type MO5F, Wl, W
2...Embedded channel type FIT0 Name of agent Patent attorney Toshi Nakao and 1 other person10
1-P next year's edition~Saka vt, vz--One surface taste potato MLr-10SFE Ding wt, wz--First year vLFET 1st figure 1-yL [= Kochua XiU To Figure 2 Figure 3 t 30Z 303 Figure 4

Claims (2)

[Claims] (1) Forming a multilayer active layer having at least one MOSFET, and MOS in the second or higher active layer
All of the FETs are of the buried channel type, and the conductivity types of the MOSFETs located in opposing positions in a certain active layer and the active layer located above or below the active layer are configured to be opposite to each other. semiconductor device. (2) The semiconductor device according to claim 1, characterized in that the active layer includes two MOSFETs, and the two MOSFETs are configured to have opposite conductivity types.