JPS6215852A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent erroneous operations even if isolation is provided only by a substrate and a thin insulating layer, by providing a second conducting type region on a first conducting type substrate directly beneath the substrate region of a thin film MIS transistor, and providing the same potential for said region and the source region of the thin film MIS transistor. CONSTITUTION:On a first conducting P-type substrate 1, a first conducting type PMIS transistor 4 is provided through an insulating film 2. On the first conducting type substrate 1 directly beneath an N-type substrate region 10 of the transistor 4, a second conducting type region 15 is provided through the insulating layer 2. A P<+> source region 12 of said thin film MIS transistor 4 and said second conducting type region 15 are set at the same potential. For example, in a semiconductor device having a structure shown in the Figure, the P-type substrate 1 and an N<+> source region 6 in the TFNMIST 3 are at the same potential. Therefore, the interface between a P-type substrate region 5 and the insulating layer 2 is not inverted. In the TFPMIST 4, the N-type region 15 and the source region 12 are at the same potential, i.e., the regions are electrically short-circuited. Therefore, the interface between the N-type substrate region 10 and the insulating layer 2 is not inverted. Thus, erroneous operations do not occur in both the TFNMIST 3 and the TFPMIST 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an insulating layer on a semiconductor substrate and a thin film MIS transistor on the insulating layer.

[Prior art and its problems]

In recent years, technology for forming a semiconductor layer with good crystallinity on an insulating layer has been developed. Therefore, for example, a 5102 film is formed on the surface of a silicon substrate, and a high-performance thin film MIS is applied on top of it.
) It has become possible to form a land disk.

FIG. 3 shows an example of such a conventional semiconductor device.

This semiconductor device has a thin film NMIS transistor 3 (hereinafter referred to as TFN) on an insulating layer 2 formed on the surface of a P-type laminate 1.
MIST) and a thin film PMIS transistor 4 (hereinafter abbreviated as TFPMIST) are formed.

The TFNMIST 3 includes a P-type substrate region 5, an N source region 6 and an N drain region 7 formed across the P-type substrate region, and a gate oxide film 8 provided on the P-type substrate region Y. It is composed of an N agate region 9 provided on this gate oxide film.

On the other hand, TFPM I ST4 has an N-type substrate region 10,
P'drain region 11 and P'source region 12 formed with this N-type substrate region in between, and N-type substrate region 1 ().
It consists of a gate oxide film 13 provided above and a P+ gate region 14 provided on this gate oxide film.

In the semiconductor device having the above structure, TFNMIS
Consider the case where T3 and TFPMIST 4 are used in one circuit, and assume that the same potential as the N+ source region 6 of TFNMIST 3, for example, 0.sup., is applied to P-type layer plate 1. In that case, a power supply voltage, for example, 10 cm is applied to the P source region 12 of the TFPMIST 4. The P-type laminate 1, through the insulating layer 2, also serves as the gate of the TFNMIST3 and TFPMIST4. Therefore, the potential of the P-type laminate 1 is 0.
In the case of ■, TFNM I Sr3 is under normal bias conditions, so it does not affect TFNMIST3, but
The TFPMIST 4 has a bias condition that inverts the interface between the insulating layer 2 and the N-type substrate region 10 to P-type, causing the TFPMIST 4 to malfunction.

The interface between the insulating layer 2 and the N-type substrate region 10 is reversed!
Although this does not always occur, it becomes a problem especially when the thickness of the insulating layer 2 is thin or when the power supply voltage is high. For TFNMIST3, the potential of the P-type laminate 1 is lower than the potential of the N+ source region 6, which is a condition for not inverting the interface between the P-type substrate region 5 and the insulating layer 2, while for TFPM I Sr1, P-type laminate 1
The potential of N is higher than the potential of the P+ source region 12.
This is a condition in which the interface between the shaped substrate region 10 and the insulating layer 2 is not inverted. Therefore, in a semiconductor device having a structure as shown in FIG. 3, no matter what potential is applied to the P-type layer plate 1, TFNM I
It is impossible to prevent malfunctions of Sr3 and TFPMIST4 at the same time.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device having a thin film MIS transistor that does not malfunction even when it is separated from a substrate by only a thin insulating layer or when operated at a high power supply voltage.

[Structure of the invention]

The present invention provides a semiconductor device having a thin film MIS transistor of a first conductivity type provided on a substrate of a first conductivity type via an insulating layer, at least the first conductivity type thin film MIS transistor directly under the substrate region of the thin film MIS transistor. A second conductivity type region is provided on the substrate with the insulating layer interposed therebetween, and the source region of the thin film MIS transistor and the second conductivity type region are set to the same potential.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention. In this embodiment, the first conductivity type is P type, and the second conductivity type is N type. This semiconductor device has the structure shown in FIG.
An N-shaded region 15 according to the present invention is provided in the P-type substrate 1 directly under the shaped substrate region 10 with an insulating layer 2 interposed therebetween.

In a semiconductor device having such a structure, the P-type laminate 1 has a TF
The same potential as the source region 6 of NMIST 3, for example 0■,
N shadow region 15 is the source region 1 of TFPM I Sr1
It can be set to the same potential as 2, for example, IOV. In that case, since the P-type laminate 1 and the N+ source region 6 are at the same potential in the TFNMIST 3, the interface between the P-type substrate region 5 and the insulating layer 2 is not reversed. Furthermore, in the TFPMIST 4, the N shadow region 15 and the P source region 12 are at the same potential.
In other words, since it is electrically short-circuited, the N-type substrate region 1
The interface between 0 and insulating layer 2 is not reversed. Therefore, T.F.
Neither NMIST3 nor TFPMIST4 causes malfunction. .

FIG. 2 is a sectional view showing another embodiment of the invention. This semiconductor device includes an NMIS formed in a P-type layer plate 21.
A transistor (hereinafter abbreviated as NMIST) 22 and a transistor formed on an insulating layer 23 provided on the surface of the P-type laminate 1
FPMIST24.

An N+ source region 25 and an N+ drain region 26 of the NMIST 22 are formed in a P-type substrate 21, and a gate oxide film 27 is provided on the P-type layer plate 21 between these regions.
An N+ agate region 28 is provided on this gate oxide film.

On the other hand, the TFPMIST 24 includes an N type substrate region 29 and a P layer formed on the insulating layer 23 with this N type substrate region sandwiched therebetween.
It consists of a + drain region 30 and a P+ source region 31, a gate oxide film 32 provided on the N type substrate region 29, and a P' agate region 33 provided on the gate oxide film. This TFPMI S T24 is the first
It has the same structure as the TFPM 15T4 in the illustrated embodiment.

In a semiconductor device having the above structure, that is, a semiconductor device having a P-type thin film MIS transistor on a P-type substrate via an insulating film, and having an N-type MIS transistor in a part of this substrate. Also, the present invention can be practiced.

In this embodiment, as in the embodiment shown in FIG.
An N shadow region 34 according to the present invention is provided on the P type substrate 1 directly under the N type substrate region 29 of T24 with an insulating layer 23 interposed therebetween.

In a semiconductor device having such a structure, the P type substrate 21 is
The same potential as the N+ source region 25 of the MIST 22, for example 0
(2) The potential of the N shadow region 34 can be set to the same potential as the P source region 31 of the TFPMIST 24, for example, IOV. Therefore, since the NMIST 22 is under normal bias conditions, it does not malfunction.

will not malfunction.

In the above two embodiments, the first conductivity type is P type, and the second conductivity type is P type.
Although N type is taken as an example of the conductivity type, the first conductivity type is N
It is clear that a semiconductor device in which the second conductivity type is P type can also be realized.

〔Effect of the invention〕

As described in detail above, according to the present invention, the above structure prevents malfunctions in thin film MIS transistors (in which the substrate is separated only by a thin insulating layer) and in thin film MIS transistors operated at a high power supply voltage. A semiconductor device having a thin film MIS transistor that does not occur can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing an embodiment of the present invention.
FIG. 3 is a sectional view showing another embodiment of the present invention, and FIG. 3 is a sectional view showing a conventional example. 1.21・・・・・・・・・・・・P-type substrate2.
23・・・・・・・・・・・・Insulating layer 3...
・・・・・・・・・・・・・・・・・・Thin film NMIS)
Ranjisk 4.24・・・・・・・・・・・・Thin film PMIS transistor 5・・・・・・・・・・・・・・・
......P-type substrate area 6.25...
・・・・・・N+source area 7.26・・・・・・
...... N+ drain region 8, 13.2
7.32... Gate oxide film 9.28...
・・・・・・N゛Agate area 10.29・・・・・・
......N-type substrate area 11.30...
・・・・・・・・・P+ drain region 12.31・
・・・・・・・・・・・・P+ source area 14',
33・・・・・・・・・・・・P゛Agate area 15.34・・・・・・・・・・・・・・・N Shadow area 2
2・・・・・・・・・・・・・・・・・・NMI
S Transistor Agent Patent Attorney Yoshiyuki Iwasa 2

Claims (1)

[Claims] (1) In a semiconductor device having a thin film MIS transistor of a first conductivity type provided on a substrate of a first conductivity type via an insulating layer, at least A region of a second conductivity type is provided on the substrate via the insulating layer, and the thin film MI
A semiconductor device characterized in that a source region of an S transistor and a region of the second conductivity type are set to the same potential.