JPS6276680A - Gaas integrated circuit device - Google Patents

Abstract

PURPOSE:To implement a complementary type MESFET inverter, whose occupying area is very small, by forming a P-type operating layer and an N-type operating layer on a semi-insulating GaAs substrate so that they are contacted to each other. CONSTITUTION:Si ions are selectively implanted in a semi-insulating GaAs substrate at first, and an N-type operating layer 2 is formed. Then Be ions are selectively implanted, and a P-type operating layer 3 is formed. Then a WN film is formed on the substrate, and a Schottky electrode 4 is formed. With the electrode 4 as a part of a mask, Si ions are implanted selectively, and N<+> type source and drain regions 5 and 6 are formed. Similarly, Be ions are selectively implanted, and P<+> type source and drain regions 7 and 8 are formed. Thereafter, heat treatment is performed and the implanted impurities are activated. Source and drain electrodes 9 and 10 on the side of an N-channel MESFET are formed with AuGe alloy. Source and drain regions 11 and 12 on the side of a P-channel MESFET are formed with AuZn alloy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a G a
The present invention relates to AS integrated circuit devices.

(Technical disadvantages of the invention and its problems) GaAs integrated circuits are attracting attention because they can operate at higher speeds than 81 integrated circuits.

In GaAs, electron mobility is high but hole mobility is extremely low, so conventionally only n-channel MESFE
Only the T circuit has been considered.

However, since the complementary MO8 circuit of Sl has been realized as a low power consumption and high speed integrated circuit, Ga
Also in As integrated circuits, studies have begun on complementary circuits incorporating p-channel MESFETs. In this case, when designing the specific layout of the complementary MESFET inverter, it is necessary to fully consider the element structure different from that of the Sl MOSFET, i.e., the use of a semi-insulating substrate, the use of Schott 1 to key gates, etc. It is.

[Purpose of the invention]

The present invention is based on the above points, and includes a complementary MESFET inverter with an optimal layout.
The present invention aims to provide an As integrated circuit device.

[Summary of the invention]

In the GaAs integrated circuit according to the present invention, an n-type active layer and an n-type active layer are formed in contact with each other on a semi-insulating GaAs substrate, and a gate electrode of a p-channel MESFET and an n-type active layer are formed on a semi-insulating GaAs substrate.
The gate electrode of the ESFET is disposed on the surface of the n-type active layer and the n-type active layer so as to be continuous across the boundary between the two active layers, thereby configuring a complementary MESFET inverter. It is characterized by

〔Effect of the invention〕

The complementary MESFET inverter layout according to the present invention has a small footprint. The reason is as follows. , a typical MOSFET used in Si ~103 integrated circuits uses an inversion layer on the surface of the substrate as a channel.

Therefore, if the layout of the present invention is adopted in a complementary MOS inverter, n-channel MO8FET
If a channel is formed on the side, it will be electrically connected to the substrate region on the p-channel side, and if a channel is formed on the p-channel MO8FET side, it will be electrically connected to the substrate region on the n-channel MO3FET side. To avoid this, normally both gate electrodes are disposed in adjacent p and n regions so as to be parallel to each other, and these gate electrodes are laid out so as to be continuous outside the element region. Complementary MOS
In order to adopt the layout of the present invention in an inverter, means for separating both channel regions is required.

On the other hand, a GaAs MESFET does not utilize a surface inversion layer, but the active layer itself is a channel region, and its thickness is controlled by a depletion layer extending from the Schottky gate electrode side. Therefore, there is no problem as described above, and both gate electrodes can be disposed continuously without providing channel separation means. This allows the area occupied by the complementary MESFET inverter to be extremely small.

Furthermore, in the layout of the normal complementary MOS inverter described above, p-channel MO8FET and n-channel MO8FET are
Each drain in the region sandwiched between each gate Mh of ET! Ohmic to commonly connect lIR? [must be established. This makes it difficult to match masks for forming contact holes when the device is miniaturized, and thus hinders reduction in the area occupied by the complementary circuit. In the present invention,
Since the source and drain regions of each MESFET are formed on both sides of one continuous gate electrode, it is easy to form ohmic electrodes, which is also advantageous in reducing the occupied area.

On the other hand, in the present invention, since the n-type active layer and the n-type active layer are provided in contact with each other, a depletion layer is formed between the two, thereby effectively narrowing the channel width.

However, the impurity concentration of the active layer normally formed by ion implantation for digital GaAs integrated circuits is 10”/
crn3, and the width of the depletion layer formed by the pn junction is about 0.2 μm.

Further, the gate width of MESFET is generally designed to be several tens of micrometers. Therefore, the influence of the depletion layer on the channel width can be almost ignored and does not pose a problem in circuit design.

(Example of the invention) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a layout of a complementary MESFET inverter according to an embodiment, and FIG. 2, FIG. 3, and FIG. Yes. Semi-insulating GaAs with a resistivity of about 107 to 10"Ω・1
On the surface of the substrate 1, there is an n-type active layer 2 which becomes a channel region and ρ.
The active layers 2 and 3 are formed in contact with each other, and a continuous Schottky gate electrode 4 is integrally formed on the surfaces of these active layers 2 and 3, extending across the boundary between the two active layers. The Schottky gate electrode 4 is formed of, for example, a 4000 WN film. On both sides of the gate i-electrode 4, an n+ type source region 5 and drain region 6, which are higher in concentration and deeper than the active layer, and a p+ type source region 7 and drain region 8 are formed. 9 and 10 are the source and train electrodes of the n-channel MESFET, respectively;
1.12 are the sources of p-channel MESFETs,
This is the drain electrode. 13 is the drain electrode 10.1
This is the wiring that connects the two.

The specific manufacturing process of this complementary MESFET inverter is as follows. First, 3t ions were applied to a semi-insulating GaAs substrate 1 at 50 keV, 2X1.
The n-type operating layer 2 is formed by selective ion implantation under the conditions of 0'2/cm2, and then 3e ions are implanted at 30keV and 5.
By selectively implanting ions under the condition of x10''/atr2, an n-type active layer 3 in contact with the n-type active layer 2 is formed.Next, 4000 WNMIs are formed on this substrate, and a well-known photolithography technique and A Schottky gate electrode 4 having a width of 1.0 μm is formed using dry etching technology.

Next, using the game I-den If14 as part of the mask, 3
I ions were selectively implanted under the conditions of 180 keV and 3X1013/cj12 to form n'''' type source and drain regions 5.6, and Be ions were similarly implanted at 100 keV.
P+ type source and drain regions were formed by selective ion implantation under the conditions of V, 7.5 x 1012, /ctn 2.
form. Thereafter, the implanted impurities are activated by heat treatment at 800 to 850'C. and n channel M
E S F E T side source and drain electrodes 9 and 10
ALJGe alloy also allows p-channel MESFET
sauce on the side.

Drain electrodes 11 and 12 are each formed from an AuZn alloy. Finally, Au wiring 13 is formed and complementary ME
The SFET inverter is completed.

Thus, according to this embodiment, it is possible to realize a complementary MESFET inverter that occupies an extremely small area without providing wasted space such as the element valve m region.

Therefore, according to this embodiment, high integration of the GaAs integrated circuit can be achieved.

In this example, the depletion 1 due to contact between the n-type active layer and the n-type active layer is approximately 0.2 μm. Also pe
The depletion layer formed by the n+ junction is approximately 0.06 μm. Therefore, in a device with a channel width of several tens of μm, these depletion layers have little effect on the device characteristics.

Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit thereof.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the layout of a complementary MESFET inverter according to an embodiment of the present invention, and FIG.
The sectional views in FIG. 3 are the same <BB= sectional view, and FIG. 4 is the same <CC- sectional view. 1... Semi-insulating GaAs substrate, 2... N-type operating layer,
3...n-type operating layer, 4...Schottky gate electrode, 5...n++ source region, 6...n+-type drain region 7...p++ source region, 8...p+-type drain region 9.11... Source electrode, 10.12...
- Drain electrode, 13... wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] In a GaAs integrated circuit device including a complementary MESFET inverter, a p-type active layer and an n
Type operation layers are formed in contact with each other, p-channel MESF
A gate electrode of the ET and a gate electrode of the n-channel MESFET are continuously disposed on the surfaces of the p-type operating layer and the n-type operating layer across the boundary between the two operating layers, thereby forming a complementary MESFET.
GaAs characterized by comprising an inverter
Integrated circuit device.