JPS58223361A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive the improvement of the efficiency of utilizing elements by enhancing the degree of freedom of circuit arrangement by a method wherein a plurality of pieces are arranged in matrix form based on unit of FET of previously decided size, and these basic units are combined only by arbitrary numbers. CONSTITUTION:The FET 419 of unit dimensions previously decided as the basic unit, e.g. of the gate width of 5mum is arranged in matrix form on a chip. In this case, a diode is composed by using a drain 403, a gate 405, a source 406, and a low resistant ion implanted layer 402, and the gate 405 of the FET 419 corresponds to the anode, and the drain 403 to the cathode. While, the diode corresponds to the FET 418. When the gate width of FET serving as the basic unit is set at 5mum as in this case, a piece of FET of the basic unit is sufficient in forming the FET of the gate width of 4mum and 5mum, and two pieces of FETs of the basic unit can be used in parallel in forming the gate width of 10mum, the rest is based thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular to a Schottky junction gate field effect transistor (GaA, a F
The present invention relates to a master slice type semiconductor integrated circuit device using a semiconductor integrated circuit (abbreviated as ET).

Most of the conventional bipolar LSIs are for high speeds, and Gatsu MOS
Since most of the products are manufactured in small quantities compared to the above, it is extremely uneconomical to prepare a full set of masks for each LSI. Therefore, in the past, a master slice with a common diffusion mask was created, and only the wiring connection pattern was changed to generate many types of LSIs. This master slice method uses a logic gate consisting of several cells as a unit.
First, perform proper placement, and then perform a wiring program.

As an arrangement method in this case, a method has been considered in which the total wiring length is minimized and at the same time the wiring density is averaged. Among them, the so-called cluster method divides a block circuit consisting of two rows of cells and replaces gates within the same block to minimize the number of crossovers between the signal @ line, power line, and ground line. It's a method.

Figure 1 (,) shows a bipolar transistor 12.14
E CL (p:ml, tt
er CoupjedJ,ogj,c) circuit.

Transistors 12 and 14 form a differential N4fhi n such that the base voltage of transistor 12 is
When the comparison voltage of the base of transistor 1 becomes higher than the comparison voltage of the base of transistor 1,
4 is cut off, the transistor 12 becomes conductive, and the collector potential of the transistor 14 rises, so the output transistor 16 becomes conductive and a positive nozzle appears at the output OUT. In addition to the EC1-4 circuit, T T Ll path,
There are various types of circuits such as DTL circuits, T) CTT circuits, 7-rib and 70-rib circuits, etc., but due to differences in current and voltage values, the dimensions and shapes of the elements are different, and they cannot be placed with each other simply by changing the wiring connection pattern. It is impossible to change. For example, as shown in FIG. 1(b), if a mask substrate is formed by arranging the blocks 21 over the entire LSI 20, with a plurality of U paths having different dimensions as one block 21, the mask substrate Only a few specified types of circuits can be obtained.

In this way, conventional master slice LSIs have mainly been bipolar logic LSIs or 6MO8 logic LSIs.
Q ILA s L
Application is also being considered for SI.

There are two types of field effect transistors (FET): pn junction type and MOS type, which mainly use Sj, and Schottky junction type, which mainly uses QaAa, but only those to which the master slice method can be applied are currently Schottky junction type F E
T (GaABFET) only.

FIG. 2 is a conceptual diagram of the structure of a GaAsFET, in which Cr
An n-type QaA 8 layer (channel) 31 with a thickness of about 0.2 μm is placed on a semi-insulating QaA, s substrate 30 with attached
grow. The n layer outside the active part is removed by mesa etching to form drain 33 and source 34 electrodes made of gold alloy. Either of the drain 33 and the source 34 can be used as the drain or the source. In between, a Schottky gate (A1 etc.) 32 is placed and Ga
Complete As F E T.

For microwave amplification, the gate length X is 1.0 to 0.
5 μm, and the source-drain distance is extremely short at 5.0 to 2.0 μm.

FIG. 3 is a configuration diagram of the GILAS logic circuit.

QaAs logic circuit consists of FETs 103, 104, 105
and Schottky diodes 101 and 102. When the input terminal ■□ is at a high level, the Schottky diodes 101 and 102 are turned on, and the GaAs
Since a high level voltage is applied to the gate of FET 105, it turns on and the output voltage becomes ■. A positive pulse is obtained, while when the input voltage ■1 is at a low level, the Schottky diodes 101, 102 cuff 7, ! -7
Since a low level voltage is applied to the gate of the GaAs FET 105, the FET 105 is turned off and the output voltage is V. you get nothing.

FIG. 4 is a plan view of a conventional QaAa logic circuit.

The planar structure in FIG. 4 corresponds to the cross-sectional structure in FIG. 2 and the circuit configuration in the third diagram, respectively. That is, the bidirectional hatched area in FIG. 4 corresponds to the drain 33 and the source 34 in FIG. 2, and the unidirectional shaded area corresponds to the gate 32.
The input voltage terminal (1) in the figure is the terminal 201 in Figure 4, and the level shift terminal (5) is the terminal 202, the power supply (2) for the switch circuit.

is terminal 203, ground terminal is terminal 205, output voltage terminal V
. correspond to the terminals 204, respectively.

Also, in FIG. 4, the diode 101 of FIG.

102 anode to 206, 209, cathode to 20
7,211 respectively, and F E T103.

The drains of 104 and 105 are 212 and 216.

204, gates at 213, 217, 219, sources at 214, 218, 220+. :, Corresponds to the situation.

One or several logic circuit structures shown in FIG. 4 are used as a basic unit, and this is called a block. Conventional Qa
Ae frill logic circuit is gold circuit star slicing method L
In the SI, a plurality of these block units are arranged and wiring is changed between the blocks to connect a plurality of logic circuits and provide various functions.

That is, in the master slice type LSI, the fifth
As shown in the figure, blocks 302 serving as basic units are arranged in a matrix on a chip 301 as a mask substrate, and a first... Connections are made through the second or δ-th wiring layers 303 and 304 to determine the logic and circuit configuration of the entire chip.

However, in the conventional master slice chip configuration,
As described above, since the basic unit is a block constituting a certain logic circuit, the type of mask substrate is limited to a specific type. For example, it is not possible to incorporate a memory of a different type from a logic circuit, a 7-lip-flop, etc. into one chip, and two types of basic elements, namely G
Since a block is constructed from a combination of an aAS FET and a Schottky diode, and the circuit layout is standardized, it is not possible to construct an arbitrary circuit. Therefore, in the conventional master slicing method, the utilization efficiency of elements is extremely poor.

Purpose of the Invention The purpose of the present invention is to improve such conventional drawbacks by making it possible to configure any type of circuit at any location on a chip, increasing the degree of freedom in circuit arrangement, and increasing the efficiency of element utilization. An object of the present invention is to provide a master slice type semiconductor integrated circuit device that can perform the following steps.

In order to achieve the above object, the semiconductor integrated circuit device of the present invention has a structure in which a plurality of field effect transistors of a predetermined size are arranged in a matrix as a basic unit in an LSI formed on a substrate. However, the present invention is characterized in that an arbitrary number of these basic units are combined to form 4 field effect transistors and diodes of arbitrary dimensions.

Embodiment of the Invention FIG. 6 shows a GILA [! FIG. 2 is a plan view of a logic circuit.

While the conventional master slice method uses a block constituting a certain logic circuit as a basic unit, the master slice method of the present invention uses one FET as a basic unit and arranges a plurality of them on a chip. That is, in the present invention, the LSI can be built using only the most frequently used FET in the circuit.
Since this FET is also used as a Schottky diode, the efficiency of use of the device can be improved.

The basic unit that governs the LSI of the present invention, that is, one FET, should be unified to a single dimension that is frequently used on a plane, a dimension that is the greatest common divisor, or two or more types of various dimensions. You can choose one or whatever you want. As described above, the present invention has a feature in the planar shape arrangement of the FET, and when viewed in cross section, there is no difference from the conventional GaAs FET, and the manufacturing process is the same as explained in Fig. 2. be. In FIG. 2, when the FET is used as a Schottky diode, the gate 32 is the anode, the drain 33 and the source 34.
Either one or both of these are used as a cathode.

FIG. 6 shows a case where a GaAs logic circuit not shown in FIG. 3 is constructed by the master slice method of the present invention. In FIG. 6, when FETs 419 of a single dimension predetermined as basic units are arranged in a matrix on a chip, the GELAE of FIG.
1 shows a method of configuring an I logic circuit. In FIG. 6, a drain 403, a gate 405, a source 406,
FET41Q consisting of N-type low resistance ion implantation layer 402
The diode 101 in FIG. 3 is constructed using F.
The gate 405 of ET419 is the anode, the drain 40
3 corresponds to the cathode. In addition, the diode 102 in FIG. 3 is connected to the FET 418 in FIG.
103 is the basic unit FETs 407 and 41 connected in parallel.
2, FET 104 in FIG. 3 is a basic unit FET 413 and 414 connected in parallel, and FET 105 in FIG. 3 is a basic unit FET 415, 416 connected in parallel.
．． 417, respectively. Furthermore, the input voltage terminal V1 in FIG. Power supply terminal V1 of the level shift circuit.
.

Switch circuit power supply terminal VD + ground terminal, output voltage terminal V. are terminals 401, 409, 410°408, respectively.
, 411.

As mentioned above, the gate length of GnA, s FET is 1.0 to 0.5 μm, but the gate width is 4 μ” +
There are various types such as 5/1m + 10μrn, 20μIn, etc., but the basic unit is the FET width) and the width is all 5
thm, F with gate widths of 4 μm and 5 μm
When making an ET, you only need one FET as the basic unit, 101
When making an FET with a gate width of 1 m, the basic part F
Two ETs may be used in parallel, and when making a FET with a gate width of 20 μm, four basic unit FETs may be used in parallel. In Figure 6, diodes 101, 102
uses FET419, 418 as the basic unit as is, and FET
Since ET103 has a gate width of 10 μm, the basic unit FETs 407 and 412 are used in parallel, and FET104 has the same gate width of <10 μm, so the basic unit FET,
Using E T 413 and 414 in parallel, FET105
has a gate width of 15 μm, so the basic unit FET4
15,416°417 are used in parallel.

(11) Also, 10 is the most frequently used size for integrated circuits.
When using a μm width FET as a basic unit,
To make an FET with a gate width of 20 μm, use two basic FETs in parallel, and create an FET with a gate width of 5 μm.
To make T, it is sufficient to use two basic unit FETs in series. Note that the gate width can be varied depending on how the circuit is designed. For example, the gate width can be changed by changing constants such as current value and resistance value, or by changing the logic values of high level and low level.

FIG. 7 is an overall configuration diagram of a chip showing an embodiment of the present invention.

The chip 501 is constituted by a mask substrate δ◯ on which one FET 502 serving as a basic unit is regularly arranged. The area 503 is an area in which the G11LA8 logic circuit shown in FIG. 0 is configured, and the FET 103 shown in FIG.
, 104, 105 are basic units, and are constructed by connecting two or three FETs 502 in parallel. Although a logic circuit can be formed anywhere on the mask substrate 504, the seventh
02) in the figure shows a case where a logic circuit is formed at the bottom of the master board 504. Single size FET on chip 501
A master board 504 arranged on the entire surface or partially of
Various circuits can be constructed in any location simply by changing the wiring layer.

For example, not only a GaAs logic circuit but also a 7-rib flop circuit, an inverter circuit, a memory circuit, etc. can be configured on the same chip 501.

Note that the gate width of the FET, which is the basic unit, can be the greatest common divisor or the most frequently used size, and even 211! It can also be made larger in size.

As described in detail, according to the present invention, in a master slicing LSI formed on a semiconductor substrate, FETs of a predetermined size are arranged in a matrix as basic units and used as a mask substrate. , it is possible to configure any circuit at any location on the chip, increasing the degree of freedom in circuit arrangement and improving the efficiency of element utilization.

[Brief explanation of drawings]

Figure 1 shows a conventional ECL circuit composed of bipolar transistors, its ECT, and a master board whose basic units are circuit blocks. Figure 2 shows a master board using QaAs F
Fig. 3 is a structural diagram of a GaAl1 logic circuit, Fig. 4 is a planar structural diagram of a conventional GaAs logic circuit, and Fig. 5 is a conventional mask-sliced LSI chip in which blocks are arranged. FIG. 0 is a plan view of a GaAs logic circuit according to an embodiment of the present invention, and FIG. 7 is a plan view of an entire LSI chip using a mask slicing method according to an embodiment of the present invention. 412-419,407,502: Basic unit F E
T. 403; drain, 405: gate, 400: source, 401 = input voltage terminal, 408: ground terminal, 409;
Power supply terminal of level shift circuit, 410: Power supply terminal of switch circuit, 411; Output voltage terminal, 501 = chip, 5
04: Master board, 503: Logic circuit area. Figure 1 fa) Figure 3~'1. VD Figure 4 Figure 2

Claims (1)

[Scope of Claims] (1) In a master slice type semiconductor integrated circuit device formed on a GaAs substrate, a plurality of field effect transistors of predetermined dimensions are arranged in a matrix as a basic unit, and the basic unit is A semiconductor integrated circuit device characterized in that any number of semiconductor integrated circuit devices can be combined at any location to form various circuits of any size. ? ) The basic unit field effect transistor is characterized in that the gate is used as an anode and one or both of the drain and the source are used as cathodes to form a Schottky diode. Semiconductor integrated circuit device. (3) The semiconductor integrated circuit device according to claim 1, wherein the basic unit field effect transistor has dimensions that are frequently used in integrated circuits or dimensions that are the greatest common divisor.