JPS6225425A - Etching method for surface protective film - Google Patents

Etching method for surface protective film

Info

Publication number
JPS6225425A
JPS6225425A JP16449985A JP16449985A JPS6225425A JP S6225425 A JPS6225425 A JP S6225425A JP 16449985 A JP16449985 A JP 16449985A JP 16449985 A JP16449985 A JP 16449985A JP S6225425 A JPS6225425 A JP S6225425A
Authority
JP
Japan
Prior art keywords
film
exposed
oxide film
resist
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16449985A
Other languages
Japanese (ja)
Inventor
Shigeru Tsuda
津田 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP16449985A priority Critical patent/JPS6225425A/en
Publication of JPS6225425A publication Critical patent/JPS6225425A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To improve the step coverage of a metal electrode by plasma etching a nitride film with a resist as a mark and chemically etching an oxide film when forming a hole after laminating the oxide film and the nitride film on a semiconductor element, thereby forming a step in the hole. CONSTITUTION:An oxide film 2 and a nitride film 3 are laminated to become a surface protective film on an Si substrate 1, a resist 4 of the prescribed shape is formed on the film 3 to be exposed with CF4+O2 plasma gas 5, and the exposed portion of the film 3 is first removed. After a tapered part is formed at the edge of the film 3 in this manner, the resist 4 is removed, and a resist 6 is again coated from the remaining part of the film 3 to the edge of the exposed film 2. Thereafter, the exposed part of the film 2 is removed by etching with fluoric acid solution, a tapered part is formed at the edge of the film 2 which similarly remains, and an aluminum electrode film 7 is coated from the remaining film having the step to the exposed surface of the substrate 1.

Description

【発明の詳細な説明】[Detailed description of the invention] 【発明の属する技術分野】[Technical field to which the invention pertains]

本発明は、半導体素体の表面に形成された酸化膜の上に
窒化膜を被着したのち、電極接触のための開口部を設け
るために行なう半導体表面保護膜のエツチング方法に関
する。
The present invention relates to a method of etching a semiconductor surface protection film in order to provide an opening for electrode contact after a nitride film is deposited on an oxide film formed on the surface of a semiconductor body.

【従来技術とその問題点】[Prior art and its problems]

半導体素体に形成される接合の露出部の保護に対して工
程中に表面に形成される酸化膜では十分でないので、そ
の上にさらに窒化膜を被着することが行われる。このよ
うに半導体素体に金属を極を設けるためには、vA縁性
である積層された酸化膜と窒化膜を除去して半導体素体
を露出させなければならない、このため、従来は窒化膜
被着の前に酸化膜を選択エツチングし、次いで全面に窒
化膜を被着してから窒化膜を選択的にプラズマエツチン
グしていた。しかしこの場合酸化膜のエツチング部はテ
ーバが生じないため、そのあと形成されるアルミニウム
電橋が酸化膜の縁部で密着せず、いわゆるステップカバ
ーレージの問題があった。
Since the oxide film formed on the surface during the process is not sufficient to protect the exposed portion of the junction formed in the semiconductor element, a nitride film is further deposited thereon. In order to provide a metal pole on a semiconductor body in this way, it is necessary to remove the stacked oxide film and nitride film, which are vA-related, to expose the semiconductor body. Prior to deposition, the oxide film was selectively etched, a nitride film was then deposited on the entire surface, and the nitride film was selectively plasma etched. However, in this case, since the etched portion of the oxide film does not have a taper, the aluminum electric bridge that is subsequently formed does not come into close contact with the edge of the oxide film, resulting in the problem of so-called step coverage.

【発明の目的】[Purpose of the invention]

本発明は、これに対して半導体素体の表面に形成された
酸化膜上に窒化膜を被着してなる表面保護膜の、開口部
の縁部における金属′r4極のステップカバーレージを
良好にすることのできるエツチング方法を提供すること
を目的とする。
In contrast, the present invention improves the step coverage of the four metal poles at the edge of the opening of the surface protective film formed by depositing a nitride film on the oxide film formed on the surface of the semiconductor element. The purpose of the present invention is to provide an etching method that can be used for etching.

【発明の要点】[Key points of the invention]

本発明は、窒化膜をマスクを介してプラズマエツチング
し、露出した酸化膜をプラズマに接触させ、マスクを介
して酸化膜を化学エツチングすることにより上記の目的
を達成する。
The present invention achieves the above object by plasma etching the nitride film through a mask, bringing the exposed oxide film into contact with the plasma, and chemically etching the oxide film through the mask.

【発明の実施例】[Embodiments of the invention]

第1図(8)〜(elは本発明の一実施例の工程を示す
もので、シリコン板1は酸化膜2.窒化膜3の2層構造
の表面保護膜を有す、(a)図はこの表面保護膜上にレ
ジスト4によりマスクを形成し、(CF4+O2)プラ
ズマガス5にさらしてエツチングする状態を示す、この
結果Cb1図に示すように窒化膜3は縁部がテーパ状に
エツチングされる0次いで(c1図に示すようにレジス
ト4を除去してあらためてレジスト6によりマスクを形
成する。(d)図は弗酸水溶液により化学エツチングし
た状態を示し、酸化膜2も縁部がテーパ状にエツチング
されている。 これは+81図に示したプラズマエツチング時に露出し
た酸化膜2もプラズマ5の影響を受け、酸化膜の表面に
近い部分がエツチングされやすくなっているためと思わ
れる。従ってこのあと+61図のようにアルミニウム電
極膜7を被着した場合、二段に形成されたテーパを有す
る段差部に電極膜は良好なステップカバーレージを示す
FIGS. 1(8) to 1(el) show the steps of an embodiment of the present invention, in which the silicon plate 1 has a surface protection film with a two-layer structure of an oxide film 2 and a nitride film 3, FIG. 1 shows a state in which a mask is formed on this surface protective film using a resist 4 and exposed to (CF4+O2) plasma gas 5 for etching. As a result, the edges of the nitride film 3 are etched into a tapered shape as shown in Figure Cb1. (c) As shown in Figure 1, the resist 4 is removed and a mask is formed again using the resist 6. Figure (d) shows the state of chemical etching with a hydrofluoric acid aqueous solution, and the oxide film 2 also has a tapered edge. This seems to be because the oxide film 2 exposed during plasma etching shown in Figure +81 is also affected by the plasma 5, and the parts near the surface of the oxide film are more likely to be etched. Also, when the aluminum electrode film 7 is deposited as shown in Figure 61, the electrode film exhibits good step coverage at the step portion having the two-step taper.

【発明の効果】【Effect of the invention】

本発明は、酸化膜とその上の窒化膜とからなる2N表面
保護膜に開口部を設ける際、窒化膜をプラズマエツチン
グすると同時に酸化膜をプラズマガスにさらすことによ
り、そのあとの酸化膜の化学エツチングの際にテーパ面
の形成を可能にしたもので、開口部の半導体表面に接触
するQ 4m膜が表面保fil膜縁部における段差部に
おいて良く密着するため、半導体素子の信転性を大幅に
改善することができる。
In the present invention, when forming an opening in a 2N surface protective film consisting of an oxide film and a nitride film thereon, the oxide film is exposed to plasma gas at the same time as the nitride film is plasma etched. This allows the formation of a tapered surface during etching, and the Q4m film that contacts the semiconductor surface in the opening adheres well to the stepped portion at the edge of the surface protective film, greatly improving the reliability of the semiconductor element. can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の工程を順次示した要部断面
図である。 1:シリコン板、2二酸化膜、 3:窒化膜、4.6:
l/シスト、5 :  (CF4 +Oりプラズマ、7
:AI電極膜。
FIG. 1 is a sectional view of a main part sequentially showing the steps of an embodiment of the present invention. 1: Silicon plate, 2 Dioxide film, 3: Nitride film, 4.6:
l/cyst, 5: (CF4 + O plasma, 7
:AI electrode film.

Claims (1)

【特許請求の範囲】[Claims] 1)半導体素体表面に形成された酸化膜上に窒化膜を被
着したのち開口部を設ける際に、窒化膜をマスクを介し
てプラズマエッチングし、露出した酸化膜をプラズマガ
スに接触させ、次いでマスクを介して酸化膜を化学エッ
チングすることを特徴とする表面保護膜エッチング方法
1) After depositing a nitride film on the oxide film formed on the surface of the semiconductor element, when forming an opening, the nitride film is plasma etched through a mask, and the exposed oxide film is brought into contact with plasma gas; A surface protective film etching method characterized in that the oxide film is then chemically etched through a mask.
JP16449985A 1985-07-25 1985-07-25 Etching method for surface protective film Pending JPS6225425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16449985A JPS6225425A (en) 1985-07-25 1985-07-25 Etching method for surface protective film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16449985A JPS6225425A (en) 1985-07-25 1985-07-25 Etching method for surface protective film

Publications (1)

Publication Number Publication Date
JPS6225425A true JPS6225425A (en) 1987-02-03

Family

ID=15794317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16449985A Pending JPS6225425A (en) 1985-07-25 1985-07-25 Etching method for surface protective film

Country Status (1)

Country Link
JP (1) JPS6225425A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH026867A (en) * 1988-06-25 1990-01-11 Kaken Kogyo Kk Treating agent for water circulating in wet coating booth and method for recovering paint with same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH026867A (en) * 1988-06-25 1990-01-11 Kaken Kogyo Kk Treating agent for water circulating in wet coating booth and method for recovering paint with same

Similar Documents

Publication Publication Date Title
EP0100735B1 (en) Lift-off process for fabricating self-aligned contacts
JPS61226929A (en) Formation of semiconductor device
GB1487546A (en) Semiconductor devices
JP2822430B2 (en) Method of forming interlayer insulating film
JPS6225425A (en) Etching method for surface protective film
JPS60220976A (en) Method of producing semiconductor device
JPH0428231A (en) Manufacture of semiconductor device
JP3323264B2 (en) Method for manufacturing semiconductor device
JPS61141158A (en) Formation of bump electrode
JPS6242435A (en) Formation of electrode
JPH05251443A (en) Manufacture of semiconductor device
JPS5918690A (en) Hall element
JPS61141157A (en) Manufacture of semiconductor element
JP3417829B2 (en) Method for manufacturing semiconductor device
JPS6214453A (en) Manufacture of semiconductor device
JPS5825229A (en) Manufacture of semiconductor device
JP2750737B2 (en) Method for manufacturing semiconductor device
JPS6193629A (en) Manufacture of semiconductor device
JPH04264733A (en) Formation of bump base film for integrated circuit device
JPS6362104B2 (en)
JPH03295243A (en) Manufacture of semiconductor device
JPS60154539A (en) Forming process of aluminium wiring
JPH10308397A (en) Electrode terminal and manufacture therefor
JPH01108726A (en) Manufacture of semiconductor device
JPS628030B2 (en)