JPS6224816B2 - - Google Patents

Info

Publication number
JPS6224816B2
JPS6224816B2 JP56189311A JP18931181A JPS6224816B2 JP S6224816 B2 JPS6224816 B2 JP S6224816B2 JP 56189311 A JP56189311 A JP 56189311A JP 18931181 A JP18931181 A JP 18931181A JP S6224816 B2 JPS6224816 B2 JP S6224816B2
Authority
JP
Japan
Prior art keywords
register
digit
digits
multiplicand
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56189311A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5892037A (ja
Inventor
Takafumi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18931181A priority Critical patent/JPS5892037A/ja
Publication of JPS5892037A publication Critical patent/JPS5892037A/ja
Publication of JPS6224816B2 publication Critical patent/JPS6224816B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
JP18931181A 1981-11-27 1981-11-27 演算処理装置 Granted JPS5892037A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18931181A JPS5892037A (ja) 1981-11-27 1981-11-27 演算処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18931181A JPS5892037A (ja) 1981-11-27 1981-11-27 演算処理装置

Publications (2)

Publication Number Publication Date
JPS5892037A JPS5892037A (ja) 1983-06-01
JPS6224816B2 true JPS6224816B2 (enrdf_load_stackoverflow) 1987-05-30

Family

ID=16239220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18931181A Granted JPS5892037A (ja) 1981-11-27 1981-11-27 演算処理装置

Country Status (1)

Country Link
JP (1) JPS5892037A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479567B1 (en) 2000-03-03 2002-11-12 Ashland Inc. Furan no-bake foundry binders and their use

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5569850A (en) * 1978-11-22 1980-05-26 Toshiba Corp Decimal multiplication system

Also Published As

Publication number Publication date
JPS5892037A (ja) 1983-06-01

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