JPS62247460A - Instruction control system - Google Patents

Abstract

PURPOSE:To ensure the effective application of a pipeline by deciding the number of stages of a control register according to an optimum number of stages obtained from the number of cycles counted in a period between a time point when the pipeline is started and the write mode of a vector register and the optimum number of stages and the access timing cycle of a bank of the vector register. CONSTITUTION:A period covering the starting point of an access pipeline 1 and/or an arithmetic pipeline 3 through the writing time point of a vector register 2 is referred to as N together with the access timing cycle of the register 2 as T respectively. Under such conditions, the number of stages of a control register 4 and/or 5 which controls the state of the instruction in the pipeline 1 and/or 3 is set at P as shown in an equation. The number of stages of the register 4 is obtained from the number of cycles counted in a period between the starting time point of the pipeline and the access timing cycle of the bank of the register 2. Thus it is possible to form a pipeline with an instruction control register having the minimum number of stages, i.e., the optimum number of stages to attain the effective application of pipelines.

Description

[Detailed Description of the Invention] [Summary] The present invention reduces the number of stages of management registers in the pipeline in instruction control of the access pipeline or the arithmetic pipeline of a vector processing device in order to reduce the idle timing of the pipeline. The configuration is configured with the optimal number of stages determined from the number of cycles from the time it is started until writing to the vector register and the access timing cycle of the vector register bank, and this allows effective use of the pipeline. Become.

[Industrial Field of Application] The present invention relates to an instruction control method in a pipeline of a vector processing device.

A vector processing device is a processing device that can perform a large amount of scientific and technical calculations, especially matrix calculations, at high speed, and uses a pipeline method in which processing units are divided into small units and processed one after another in an assembly line method.

Vector processing devices are increasingly required to improve their processing speeds, and in order to do so, it is first necessary to operate each pipeline as continuously as possible. To achieve this, an instruction control method is required to supply instructions to the pipeline without interruption.

BACKGROUND TECHNOLOGY FIG. 3 is a block diagram showing the configuration of a conventional example, and shows portions related to the present invention extracted from a vector processing device and a main storage device.

In the figure, l indicates one or more access pipelines, and data is transferred between the main memory section consisting of a main memory unit (MSU) and a main memory control unit (MCU) and a vector register (VR) 2. Make a transfer.

Reference numeral 3 denotes one or more arithmetic pipelines, which perform arithmetic operations while reading data from the vector register (VR) 2 and send the results to the vector register (VR) 2.
write to.

4 is a management register for the access pipeline;
is a management register for the calculation pipeline.

Conventionally, these management registers 4 and 5 have two stages: (1) an R stage indicating that the pipeline is in the process of reading data; and (2) an S stage indicating that the pipeline is in the process of transferring or calculating data.
It consisted of three stages: stage 1, and W stage, which indicates that data or operation results are being written to the vector register (VR) 2.

In the R stage, the value is held from the time the instruction is input to the management register until at least the data reading is completed, and continues to be held until the value transitions to the S stage.

In the S stage, the value received from the R stage is held until the writing of the vector register is started.

When writing to the vector register is started, the instruction in the S stage transitions to the W stage, and the S stage becomes ready to accept new instructions.

In the W stage, the value continues to be held until writing to the vector register is completed.

FIG. 4 is a time chart showing the operating status of the management register according to the conventional example. The operation of the pipeline and management register is explained below.

First, when the first instruction A is input to the R stage, the data is read out, and since the S stage is empty in the initial state, it is immediately moved to the S stage, and is held until the operation or data transfer with the main memory is completed. be done.

When the operation or data transfer is completed, the instruction A is transferred to the W stage, the S stage becomes ready to receive the next instruction B, and the instruction B is transferred from the R stage to the S stage.

At the W stage, when the writing of the data for the instruction to the vector register is completed, the instruction B can be accepted, the instruction B is transitioned, and the data of the instruction B is written.

In the S stage, after the instruction B is transitioned, the instruction C is transitioned, the operation or data transfer of the instruction C is performed, and this is held until the end. In other words, instruction C does not enter S stage until instruction A finishes writing data and instruction B transitions from the S stage.
It is placed in a stage to start an operation or data transfer, and is held until the end.

Therefore, as shown in the figure, instructions that may be executed continuously are executed intermittently.

[Problems to be Solved by the Invention] As explained above, in the conventional configuration, instructions that can be executed consecutively create spaces in the pipeline due to the limit on the number of stages of management registers. There were cases where it was not being used effectively.

The present invention aims to provide a new command control system that solves these conventional problems.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the command control system of the present invention.

In FIG. 1, the same reference numerals as in FIG. 3 indicate the same objects.

The management register for the access pipeline has an access timing cycle of a bank of vector registers as T, and
When the access timing time from the start of the access pipeline to the start of writing to the vector register is N1, the number of stages P1 is expressed by the following equation (1) or (2).

P+ =N+ /T+ l・−・−・−・−・−・−・
・−・・・・・・(1) (When N+/T is an integer) P + = (N I/T) + 2−−−−−−−
−1・・−・−・・(2) (When N+/T is not an integer, here, [ ] is a Gaussian symbol, and indicates the integer closest to it without exceeding the quotient in [ ].) Arithmetic pipe Regarding the line management register, similarly, when the access timing time from the start of the calculation pipeline to the start of writing to the vector register is N2, the number of stages is expressed by the following equation (3) or (4). It consists of P2.

P2 =N2 /T+ 1-・--1111-...
−111−−−−・・−・・−(3) (When N2/T is an integer) P2− (N2 /T)+ 2−・・−・−・−−−−
−−・−・・−(4) (When N2/T is not an integer) [Effect] If the read for one instruction ends within the access timing period T of the bank of the vector register, successive reads will occur. It takes N1 +T in the access pipeline and N2 +T in the arithmetic pipeline from when the instruction is started until the instruction is completed.

At this time, execution of the command is started every cycle T at the most troublesome time.

Therefore, in the access pipeline management register, N
When l+T is divisible by T, prepare the number of stages equal to the quotient of N and +T divided by T, and when Nl +T is not divisible by T, prepare the stage number of ((Nl +T)/T) + 1 stage. You can handle this by preparing .

For the management register of the arithmetic pipeline, for the same reason, when N2 +T is divisible by T, (N2
+T)/T stages are prepared, and if it is not divisible, a ((N2 +T)/T)+1 stage is prepared.

As described above, according to the instruction control method of the present invention, the number of stages of the management register is determined from the number of cycles from the start of the pipeline to the start of writing to the vector register and the access timing cycle of the bank of the vector register. Since it is a value, it is configured with the minimum number of stages, that is, the optimum number of instruction management registers to use the pipeline without any vacant space.

[Example] The present invention will be described in more detail below with reference to an example shown in FIG.

FIG. 2 is a time chart showing the operating status of the management register according to the embodiment of the present invention.

In this embodiment, the number of cycles from the start of the access pipeline to the start of data writing to the vector register is 3.5 cycles, that is, N1-3,5T.

Therefore, according to the above equation (2), it becomes P+ -5,
The management register consists of five stages.

5 stages, R, S+, 32. We will call them S,,W.

The operation of the pipeline and management register will be described below with reference to FIG.

(1) The first instruction A is input to the R stage.

(2) Since each stage is empty in the initial state, the instruction A
is transferred to the SI stage after one clock, then transferred to the S2 stage after one clock, and then transferred to the S2 stage after one clock.
Transitioned to 3 stages and held. Data transfer according to instruction A is started.

(3) In the next cycle, the second instruction B is input to the R stage, and the Sl stage and S2 stage are empty, so
After one clock, it is transited to the Sl stage, and after one clock, it is transited to the S2 stage, where it is held, and data transfer according to instruction B is started.

(4) In the next cycle, the third instruction C is input to the R stage, and since the S1 stage is empty, it is immediately transferred to the S1
A transition is made to the stage, and data transfer according to instruction B is started.

(5) In the next cycle, the fourth instruction is input to the R stage, and writing by instruction A starts in the middle of the cycle, so the instruction A in the 83rd stage is transferred to the W stage, and writing to the vector register is started. It will be done. Also, S3
Since it is recognized that the stage is empty, instruction B is transitioned to the S3 stage, instruction C is transitioned to the S2 stage, and instruction A is transitioned to the Sl stage.

(6) In the next cycle, the fifth instruction E is input to the R stage, and at the same time as instruction A finishes writing data to the vector register in the middle of the cycle, instruction B starts writing data to the vector register. So,
Instruction B in the S3 stage is transferred to the W stage. S3
Since it is recognized that the stage is vacant, instruction C is transferred to the S3 stage, instruction C is transferred to the S2 stage,
Instruction E is transitioned to the S+ stage.

(7) In the next cycle, data writing to the vector register by instruction B is completed in the middle of the cycle, and instruction C in the S3 stage is transferred to the W stage and writing to the vector register is performed. The instruction E is transferred to the S] stage, and the instruction E is transferred to the S2 stage.

As described above, an instruction can be input to the R stage every cycle T, and the pipeline operates effectively without interruption.

The access pipeline management register has been explained above, but the arithmetic pipeline can similarly operate without interruption by setting the arithmetic pipeline management register to P2 = (N2 /T) + 2 stages. .

[Effects of the Invention] As explained above, according to the present invention, the number of stages of management registers is optimized, waiting for the S stage does not affect the R stage, and instruction processing efficiency is increased. The practical effects are extremely large.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a time chart showing the operation of a management register according to an embodiment of the present invention, Fig. 3 is a block diagram showing the configuration of a conventional example, and Fig. 4 is a conventional example. 5 is a time chart showing the operation of a management register. In the drawing, l is an access pipeline, 2 is a vector register (VR), 3 is an arithmetic pipeline, 4 is an access pipeline management register, 5 is an arithmetic pipeline management register, MCU is a main memory control unit, MSU, are the main storage device and , respectively. Principle block diagram of the present invention RSI S2 SI W Time chart showing the operation of the management register according to the embodiment of the present invention Figure 2 Block diagram showing the configuration of the conventional example 183 Figure: l) l1
] l 1 ] 1 Time chart No. 4 showing the operation of the management register according to the conventional example
figure

Claims (1)

[Claims] A vector register (2
), and one or more access pipelines (1) that transfer data between the vector register (2) and the storage device.
), and one or more calculation pipelines (3) for performing calculations while reading data from the vector register (2) and writing the results to the vector register (2), the vector processing device comprising: Let N be the time from the start of the access pipeline (1) and/or the calculation pipeline (3) to the time of writing to the vector register, and
), the number of stages of management registers (4 and/or 5) that manage the states of instructions in the access pipeline (1) and/or the operation pipeline (3) is: An instruction control system characterized in that it is configured such that P is expressed by the following formula. P=N/T+1 (when N/T is an integer) P=[N/T]+2 (when N/T is not an integer) (However, [ ] is a Gaussian symbol.)