JPH0118456B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data alignment circuit that arranges the plurality of bytes of data in a form suitable for an arithmetic circuit in an information processing apparatus that processes predetermined plurality of bytes of data as one unit.

Generally, in this type of information processing device, as shown in FIG.
When processing byte data, the byte position within the 4-byte unit of this data does not match the input byte position of the arithmetic circuit, so it is necessary to rearrange it in a form that is suitable for the arithmetic circuit. It is necessary to perform alignment. As shown in FIG. 1, the conventional alignment method is to first divide data into two pieces of data in units of multiple bytes and transfer the data in two stages. This 2
The data transferred over the stages is applied to a conventional data alignment circuit shown in FIG.
The data for the first time is held in register 1, and the data for the second time is held in register 2. Then, add these data to the byte-by-byte shift circuit 3,
The position of the first byte of valid data in register 1 is shifted according to the contents of register 4, which indicates the position, and arranged in the required form. However, this method has the disadvantage that it is necessary to hold even data that is not actually needed, and that the number of input signals to the shift circuit itself is large.

An object of the present invention is to provide an economical data sorting circuit that can sort multiple bytes of data in a form suitable for an arithmetic circuit without retaining unnecessary data.

According to the present invention, in order to process a predetermined plurality of bytes of data existing astride a predetermined boundary as one unit of information, the first half of the plurality of bytes of data that straddles the boundary is included. A predetermined number of bytes of data is transferred as first data, and data of the same number of bytes as the first data, including the latter half of the plurality of bytes of data that straddles the boundary, is transferred to the first data. In an information processing apparatus that transfers and processes data for the second time following the first data, a first register that selectively sets or holds the plurality of bytes of data;
a second register that indicates the first byte of data in the register; and a selection circuit that changes the byte position in response to the plurality of bytes of data held in the first register, For the second data, all bytes of the first register are set as is, and for the second data, the data contained in the first data of the first register is set according to the instruction of the second register. The selection circuit sets the last byte of the first data held in the first register and the second data held in the first register by the selection circuit. The byte position is changed so that the first byte of the data is continuous with the first byte of the data.

Next, regarding the data alignment circuit according to the present invention,
This will be explained with reference to the drawings.

FIG. 3 shows the configuration of an embodiment according to the present invention, taking as an example the case where 4-byte data is processed as one unit. In the figure, 11 is a 4-byte register with a partial write function, 12 is a 2-bit register that holds the first byte position of the data in register 11, and 13 receives the data in register 11 and makes it the contents of register 12. This is a selection circuit for selectively changing the byte position. The details of the partial write operation of the register 11 are shown in FIG. 4, and the details of the operation of the selection circuit 13 are shown in FIG. In addition, S in FIG. 4 indicates a set state, H indicates a hold state, and the fifth
B0, B1, B2 and B3 in the figure indicate bytes 0, 1, 2 and 3 of register 11, respectively. First, the data transferred for the first time is
All bytes of register 11 are set as is. Next, the second transferred data is set to a specific byte or a plurality of bytes indicated by the register 12, as shown in FIG. 4, or is truncated as is. Although the data obtained here is only valid data, it is not necessarily aligned to the original byte position. Therefore, by supplying the data in register 11 to selection circuit 13 and selectively changing the byte position according to instructions from register 12, the fifth
As can be seen in the figure, data aligned to the original byte position can be obtained from the output side.
For example, taking the transfer data as shown in FIG. 1 as an example, the contents of the register 11 at the time when the second transfer data has been set are as shown in FIG. 6a. By inputting this to the selection circuit 13, rearranged data as shown in FIG. 6b is obtained from its output.

As is clear from the above description, according to the present invention, by selectively setting or holding each byte of data in one register,
2. Remove unnecessary parts of the data transferred the first time.
Since it can be rewritten with the valid data that has been transferred a second time, the number of data holding registers can be reduced without losing the validity of the data, and the conventional shift circuit can be replaced with a selection circuit. This simplifies the configuration, which has a significant effect on improving the economical efficiency of the product.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of unaligned input data, FIG. 2 is a block diagram showing an example of a conventional data alignment circuit, and FIG. 3 is a block diagram showing an embodiment of the data alignment circuit according to the present invention. FIG. 4 is a diagram showing different partial write states of the register 11 in FIG. 3;
5 is a diagram showing different states of byte position change in the selection circuit 13 shown in FIG. It is a diagram showing stored contents. In the figure, 1, 2, 4,
11 and 12 are registers, 3 is a shift circuit, and 13 is a selection circuit.

Claims (1)

[Scope of Claims] 1. In order to process predetermined multiple bytes of data existing across a predetermined boundary as one unit of information, the first half of the multiple bytes of data that straddles the boundary is A predetermined number of bytes of data is transferred as first data, and data of the same number of bytes as the first data including the second half of the plurality of bytes of data that straddles the boundary is transferred as first data. An information processing device that transfers and processes the data a second time following the first data, a first register that selectively sets or holds the plurality of bytes of data, and a first byte of the data in the first register. a second register that indicates a position; and a selection circuit that changes the byte position in response to the plurality of bytes of data held in the first register; For the second data, the data of the plurality of bytes included in the first data of the first register is set as is in all bytes of the first register. is set to a part other than the first half part, and the selection circuit selects the first
Data characterized in that the byte position is changed so that the last byte of the first data held in the register and the first byte of the second data held in the first register are consecutive. alignment circuit.