JPS5617434A - Arithmetic control system - Google Patents

Arithmetic control system

Info

Publication number
JPS5617434A
JPS5617434A JP9341179A JP9341179A JPS5617434A JP S5617434 A JPS5617434 A JP S5617434A JP 9341179 A JP9341179 A JP 9341179A JP 9341179 A JP9341179 A JP 9341179A JP S5617434 A JPS5617434 A JP S5617434A
Authority
JP
Japan
Prior art keywords
ram14
ram13
adder circuit
gate
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9341179A
Other languages
Japanese (ja)
Inventor
Yutaka Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9341179A priority Critical patent/JPS5617434A/en
Publication of JPS5617434A publication Critical patent/JPS5617434A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the memory capacity of a control part while increasing a processing speed by making it possible to perform data transfer and write processing for specific codes in the same run.
CONSTITUTION: To process data written in F-RAM13 and S-RAM14, the contents of designated registers in F-RAM13 and S-RAM14 are transferred to latch circuits 29 and 36 under the command of control part 11 and also input to input terminals (a) and (b) of adder circuit 22 by way of gate circuits 30 and 37. Adder circuit 22 processes the input data and the arithmetic results are written in F-RAM13 through gate 43 or in S-RAM14 through gate 45. In addition to arithmetic operation using adder circuit 22, data transfer from F-RAM13 to S-RAM14 or vice versa and the process of writing specific codes in a read-side memory can be performed in the same instruction cycle without using adder circuit 22.
COPYRIGHT: (C)1981,JPO&Japio
JP9341179A 1979-07-23 1979-07-23 Arithmetic control system Pending JPS5617434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9341179A JPS5617434A (en) 1979-07-23 1979-07-23 Arithmetic control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9341179A JPS5617434A (en) 1979-07-23 1979-07-23 Arithmetic control system

Publications (1)

Publication Number Publication Date
JPS5617434A true JPS5617434A (en) 1981-02-19

Family

ID=14081548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9341179A Pending JPS5617434A (en) 1979-07-23 1979-07-23 Arithmetic control system

Country Status (1)

Country Link
JP (1) JPS5617434A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0472724A (en) * 1990-07-13 1992-03-06 Sony Corp Dryetching process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0472724A (en) * 1990-07-13 1992-03-06 Sony Corp Dryetching process

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