JPS6224694A - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JPS6224694A JPS6224694A JP16285885A JP16285885A JPS6224694A JP S6224694 A JPS6224694 A JP S6224694A JP 16285885 A JP16285885 A JP 16285885A JP 16285885 A JP16285885 A JP 16285885A JP S6224694 A JPS6224694 A JP S6224694A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- insulating layer
- layer
- multilayer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は電子計算機などに使用されるLSI搭載のため
の多層回路基板とくに有機物で絶縁層を形成する薄膜多
層回路基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multilayer circuit board for mounting an LSI used in electronic computers and the like, and particularly to a thin film multilayer circuit board in which an insulating layer is formed of an organic material.
従来より多層回路基板の高精度、高機能化をはかるため
に有機絶縁層を使用することは、たとえば特開昭57−
202797号公報に記載されている。上記の公報では
有機絶縁層にポリイミドを使用してその積層法について
記載されているが、これを使用した多層基板の使用状態
に対する信頼性の配慮については何等記載されていない
。すなわち、高精度、高機能が要求される多層回路基板
の主な用途とは大形計算機のLSI搭載用多層回路板で
あるが、この場合には、信頼性の面からLSI搭載部の
気密封止が大前提である。その理由は、絶縁層形成時、
絶縁物体と、有機絶縁層との間に熱膨張の差で発生する
応力により上記両者の間に剥離しようとする力が作用す
る。この力は基板の端部で最大となり、かつ有機絶縁層
の膜厚が厚ければ厚いほど大きくなる。そのため、膜の
厚さには自ら制限を受けるからである。これに対して上
記公報に記載された構成では、基板の端部に耐湿性の劣
る有機物層を含めているため、上記の力に対抗しうる力
で気密を封止することが困難であり、あえて気密の封止
を行なうとすれば、基板の裏面を気密の封止代にしなけ
ればならないため、構成が複雑になる恐れがある。Conventionally, the use of organic insulating layers to improve the precision and functionality of multilayer circuit boards has been proposed, for example, in Japanese Patent Application Laid-Open No.
It is described in No. 202797. Although the above-mentioned publication describes a method of laminating the organic insulating layer using polyimide, it does not describe any consideration of the reliability of the multilayer substrate using this in the usage conditions. In other words, the main application of multilayer circuit boards that require high precision and high functionality is multilayer circuit boards for mounting LSIs in large computers. The main premise is to stop. The reason is that when forming the insulating layer,
Due to the stress generated between the insulating object and the organic insulating layer due to the difference in thermal expansion, a force that tends to separate them acts between them. This force is maximum at the edge of the substrate, and increases as the thickness of the organic insulating layer increases. This is because the thickness of the film is subject to its own limitations. On the other hand, in the configuration described in the above-mentioned publication, since an organic layer with poor moisture resistance is included at the edge of the substrate, it is difficult to achieve an airtight seal with a force that can counteract the above-mentioned force. If airtight sealing is to be performed, the back side of the substrate must be made into an airtight sealing area, which may complicate the configuration.
本発明は、前記従来の問題点を解決し、気密封止の容易
な高精度、高機能が可能な多層回路基板を提供すること
にある。The present invention solves the above-mentioned conventional problems and provides a multilayer circuit board that can be easily hermetically sealed, has high precision, and is highly functional.
本発明は前記の目的を達成するため、絶縁部基体の上面
の周辺部以外に絶縁層と導体層とを交互に積層し、上記
周辺部を気密封止代に形成したことを特徴とするもので
ある。In order to achieve the above object, the present invention is characterized in that insulating layers and conductor layers are alternately laminated on a portion other than the peripheral portion of the upper surface of the insulating portion base, and the peripheral portion is formed into an airtight sealing area. It is.
以下本発明の実施例を示す図面について説明する。第1
図は本発明の実施例を示す薄膜多層回路基板の製作工程
図である。同図(alに示す如く、たとえばアルミナセ
ラミック板あるいは厚膜多層配線板1上面全体にたとえ
ば日立化成工業株式会社製のビーアイキュ(PIQ)(
商品名)をスピンナにより均一に塗布し、これを熱処理
して有機絶縁層のポリイミド層20を形成する。然るの
ち、ホトレジストを用いてエツチングマスク3を形成す
る。この際、スルホール形成個所にマスク開口部40を
形成し、かつ上記厚膜多層配線板1の周端部より一定距
離50の領域のホトレジストを除去するようにする。つ
いで同図(b)に示す如く、上記エツチングマスク3を
用いてポリイミドN20をヒドラジンヒトラードおよび
エチレンジアミンの混液あるいは02プラズマなどでエ
ツチングして上記レジストを除去する。ついで同図(C
1に示す如く、半導体などで用いられる方法により配線
材の成膜。The drawings showing embodiments of the present invention will be described below. 1st
The figure is a manufacturing process diagram of a thin film multilayer circuit board showing an embodiment of the present invention. As shown in the same figure (al), for example, BIQ (PIQ) manufactured by Hitachi Chemical Co., Ltd.
(trade name) is uniformly applied using a spinner and heat-treated to form a polyimide layer 20 as an organic insulating layer. Thereafter, an etching mask 3 is formed using photoresist. At this time, a mask opening 40 is formed at the location where the through hole is to be formed, and the photoresist is removed from an area a certain distance 50 from the peripheral edge of the thick film multilayer wiring board 1. Then, as shown in FIG. 3B, using the etching mask 3, the polyimide N20 is etched with a mixture of hydrazine hydrogen hydride and ethylenediamine, or with 02 plasma, to remove the resist. Next, the same figure (C
As shown in 1, wiring material is formed by a method used in semiconductors.
ホトエツチングで配線層6を形成したのち、上記ポリイ
ミド層20と同一のポリイミド1!21を上記厚膜多層
配線板lの周端部より一定距離50の領域。After forming the wiring layer 6 by photo-etching, polyimide 1!21, which is the same as the polyimide layer 20, is coated in an area a certain distance 50 from the peripheral edge of the thick film multilayer wiring board l.
ポリイミド層20および配線層6を覆うように形成する
。ついで同図(d)に示す如く、上記ポリイミド層21
をバターニングする。このとき、上記厚膜多層配線板1
の周端部より一定距離51の領域のポリイミド層21を
除去するとともに上記配線層6に接続するマスク開口部
41を形成する。ついで同図(e)に示す如く、上記を
必要回数繰返して所定の多層回路基板を形成する。この
ときの厚膜多層配線板1の周端部よりポリイミド層21
の最下部外周部までの距離5xは上記厚膜多層配線板1
の周端部よりポリイミド層21の最下部内周部までの距
離5 (X−11より小さく、かつOにならないように
配慮する必要がある。It is formed to cover the polyimide layer 20 and the wiring layer 6. Then, as shown in FIG. 2(d), the polyimide layer 21
Buttering. At this time, the thick film multilayer wiring board 1
A portion of the polyimide layer 21 at a certain distance 51 from the peripheral edge of the polyimide layer 21 is removed, and a mask opening 41 connected to the wiring layer 6 is formed. Then, as shown in FIG. 2(e), the above steps are repeated a necessary number of times to form a predetermined multilayer circuit board. At this time, the polyimide layer 21 is
The distance 5x to the bottom outer circumference of the thick film multilayer wiring board 1 is
It is necessary to take care that the distance 5 from the peripheral edge of the polyimide layer 21 to the lowermost inner peripheral part of the polyimide layer 21 is smaller than X-11 and does not become O.
したがって本発明においては、厚膜多層配線板1の周端
部より所定距離の領域を段階的に形成し、その領域内に
有機物層を含まないように構成したものであるから、多
層化に対しても膜厚が一定になって剥離力が増大するの
を防止し、安定したかつ高機能、高信頼度の多層回路基
板を実現することができる。Therefore, in the present invention, a region is formed in stages at a predetermined distance from the peripheral edge of the thick film multilayer wiring board 1, and the region is configured so as not to contain an organic layer, so that it is difficult to increase the number of layers. Even if the film thickness is kept constant, the peeling force can be prevented from increasing, and a stable, highly functional, and highly reliable multilayer circuit board can be realized.
(発明の効果)
本発明は以上述べたる如く、多層化に対しても膜厚が一
定になるので、剥離力の増大を防止して安定したかつ高
機能、高信頼度の多層回路基板を実現することができる
効果を有する。(Effects of the Invention) As described above, the present invention maintains a constant film thickness even when multilayered, thereby preventing an increase in peeling force and realizing a stable, highly functional, and highly reliable multilayer circuit board. It has the effect of being able to.
第1図(a)〜(e)は本発明の実施例を示す多層回路
基板の製作工程図である。
1・・・厚膜多層配線板、21.22・・・ポリイミド
層、3・・・エツチングマスク、40.41・・・マス
ク開口部、50、51・・・絶縁層除去領域、6・・・
配線層。FIGS. 1(a) to 1(e) are manufacturing process diagrams of a multilayer circuit board showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Thick film multilayer wiring board, 21.22... Polyimide layer, 3... Etching mask, 40.41... Mask opening, 50, 51... Insulating layer removal area, 6...・
wiring layer.
Claims (1)
を交互に積重して形成する多層配線基板において、上記
絶縁物基体上の周端部の一定距離領域を残して有機物か
らなる絶縁層を構成したことを特徴とする多層配線基板
。 2、前記絶縁層はその総厚さ(各層毎の厚さの和)が絶
縁層の周辺部で基体周辺部方向に薄くなるように構成さ
れたことを特徴とする特許請求の範囲第1項記載の多層
配線基板。[Claims] 1. In a multilayer wiring board formed by alternately stacking an insulating layer made of an organic substance and a conductor layer on an insulating substrate, a certain distance area at the peripheral end of the insulating substrate A multilayer wiring board characterized in that an insulating layer made of an organic substance is formed by leaving the . 2. The insulating layer is configured such that its total thickness (the sum of the thicknesses of each layer) becomes thinner toward the periphery of the base at the periphery of the insulating layer. The multilayer wiring board described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60162858A JPH0714108B2 (en) | 1985-07-25 | 1985-07-25 | Multilayer wiring board and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60162858A JPH0714108B2 (en) | 1985-07-25 | 1985-07-25 | Multilayer wiring board and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6224694A true JPS6224694A (en) | 1987-02-02 |
JPH0714108B2 JPH0714108B2 (en) | 1995-02-15 |
Family
ID=15762587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60162858A Expired - Lifetime JPH0714108B2 (en) | 1985-07-25 | 1985-07-25 | Multilayer wiring board and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0714108B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH035615A (en) * | 1989-05-31 | 1991-01-11 | Kawasaki Steel Corp | Melting equipment of incineration ash |
JPH03286597A (en) * | 1990-04-03 | 1991-12-17 | Fujitsu Ltd | Circuit board of multilayer interconnection |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139996A (en) * | 1981-02-24 | 1982-08-30 | Nippon Electric Co | Hybrid multilayer circuit board |
-
1985
- 1985-07-25 JP JP60162858A patent/JPH0714108B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139996A (en) * | 1981-02-24 | 1982-08-30 | Nippon Electric Co | Hybrid multilayer circuit board |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH035615A (en) * | 1989-05-31 | 1991-01-11 | Kawasaki Steel Corp | Melting equipment of incineration ash |
JPH03286597A (en) * | 1990-04-03 | 1991-12-17 | Fujitsu Ltd | Circuit board of multilayer interconnection |
Also Published As
Publication number | Publication date |
---|---|
JPH0714108B2 (en) | 1995-02-15 |
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