JP4775753B2 - Method for manufacturing dielectric thin film capacitor - Google Patents

Description

  The present invention relates to a method for manufacturing a dielectric thin film capacitor, and more particularly to a method for manufacturing a dielectric thin film capacitor connected to an external electronic component such as a large scale integrated circuit element (LSI).

  In recent years, various electronic parts such as LSIs have been increased in density and the operation speed has been increasing.

  When the operation speed of the electronic component increases as described above, voltage noise and voltage fluctuation are likely to occur due to the switching operation of the electronic circuit.

  Therefore, conventionally, the upper electrode of the capacitor is arranged so as to be in contact with the adhesive layer and connected to the LSI, and the upper electrode and the lower electrode are connected to each other through a through hole provided through the protective film and the adhesive layer. A capacitor built-in electronic circuit connected to an LSI wiring section has been proposed (Patent Document 1).

  In Patent Document 1, the generation of a signal error due to voltage noise or the like is suppressed by incorporating a thin film capacitor having a metal oxide having a high formation temperature as a dielectric layer in a member constituting an electronic circuit. .

  By the way, the electronic circuit with built-in capacitor described in Patent Document 1 is manufactured by a method as shown in FIG.

That is, in the capacitor forming step 101, after forming a release layer made of a Cr film on a Si substrate, a first adhesive layer made of a Ti film is formed, and then a first electrode layer made of a Pt film, barium titanate. A dielectric layer made of strontium ((Br, Sr) TiO ₃ ; hereinafter referred to as “BST”) and a second electrode layer made of a Pt film are sequentially formed, and further made of a Ti film on the second electrode layer. A second adhesive layer is formed, thereby forming a capacitor (thin film capacitor) on the Si substrate.

  Next, in the substrate bonding step 102, the Ti film and the LSI are bonded through an organic adhesive sheet.

  Next, in the capacitor transfer step 103, for example, a mixed aqueous solution of hydrochloric acid and aluminum chloride is used as an etching solution, and the release layer is dissolved by a wet etching method, thereby removing the Si substrate. Since the release layer is immersed in the etching solution while being sandwiched between the rigid Si substrate and the LSI, the etching solution enters the interface between the release layer and the first adhesive layer. For this reason, by selectively applying mechanical external force such as ultrasonic vibration to the etching solution, the etching solution can easily enter the interface between the peeling layer and the first adhesive layer, and the peeling layer is selectively etched. Thereby, the Si substrate is removed, and the capacitor is transferred onto the LSI.

  In the subsequent connection step 104, a through hole is formed at a predetermined position of the protective film covering the capacitor, the organic adhesive sheet, and the first and second adhesive layers, and the capacitor and the wiring portion disposed in the LSI are connected. As a result, the circuit with a built-in capacitor disclosed in Patent Document 1 is manufactured.

  In Patent Document 1, in the capacitor forming step 101, a first adhesive layer made of a Ti film is directly formed on a Si substrate, and then a first electrode layer, a dielectric layer, a first layer are formed on the first adhesive layer. The electrode layer and the second adhesive layer are sequentially formed, and in the capacitor transfer step 103, the capacitor is transferred onto the LSI, and an aqueous potassium hydroxide solution maintained at a liquid temperature of about 80 ° C. is used as an etching solution. Also disclosed is a technique for directly dissolving a Si substrate by a wet etching method and thereby removing the Si substrate.

JP 2001-210789 A

  However, the method of dissolving and removing the release layer by the wet etching method as in Patent Document 1 has the following problems.

  That is, the Si substrate can be reused by selectively dissolving and removing only the release layer, but the mixed aqueous solution of hydrochloric acid and aluminum chloride used as the etching solution is soluble in the dielectric layer. Therefore, it is necessary to protect the dielectric layer from coming into contact with the etching solution.

  However, in Patent Document 1, since the mechanical external force such as ultrasonic vibration is applied to the etching solution as described above, the etching solution is likely to enter the dielectric layer, and the dielectric layer is in contact with the etching solution. It is difficult to protect against.

  Further, in Patent Document 1, although a mechanical external force such as ultrasonic vibration is applied to the etching solution as described above, if a large Si substrate is used for the purpose of improving productivity, the time required for etching is remarkably long. Therefore, productivity cannot be improved.

  In the method of directly forming the first adhesive layer on the Si substrate without providing the release layer on the Si substrate, the Si substrate is dissolved and removed using an aqueous potassium hydroxide solution. There was a problem.

  That is, the aqueous potassium hydroxide solution has a slow etching rate of 1 to 2 μm / min with respect to the Si substrate. For example, when a Si substrate having a thickness of 525 μm is used, the etching process requires 4 hours or more. On the other hand, when a thin Si substrate is used in order to shorten the etching processing time, the cost of the Si substrate is increased, and the Si substrate is dissolved, so that the Si substrate cannot be reused.

Further, since the SiO ₂ film remains on the first adhesive layer be removed by dissolving Si substrate, Patent Document 1, using a mixed aqueous solution of hydrofluoric acid and nitric acid as an etching solution, the SiO ₂ film Dissolved and removed. However, since this etching solution also dissolves the dielectric layer easily, it must be protected so that the etching solution does not enter the dielectric layer, which may lead to a complicated manufacturing process.

  The present invention has been made in view of such circumstances. A dielectric thin film capacitor can be manufactured with high efficiency without adversely affecting the capacitor portion, and a substrate material separated from the capacitor portion can be easily manufactured. An object of the present invention is to provide a method of manufacturing a dielectric thin film capacitor that can be reused.

In order to achieve the above object, a method of manufacturing a dielectric thin film capacitor according to the present invention includes a first capacitor portion in which a first electrode film and a second electrode film are formed to face each other with a dielectric thin film therebetween. A method of manufacturing a dielectric thin film capacitor formed on a second substrate, wherein the second electrode film, the dielectric thin film, and the second thin film are formed on a second substrate having a coefficient of thermal expansion different from that of the first substrate. A capacitor forming step of sequentially forming one electrode film to form a capacitor portion; a first resin layer forming step of forming a first resin layer so as to cover the capacitor portion on the second substrate; A second resin layer forming step of forming a second resin layer made of the same material as the first resin layer on the surface of the first substrate; the first resin layer; and the second resin layer; The second substrate and the first substrate so that the first substrate and the first substrate are in contact with each other. A joined body forming step of forming a joined body having an insulating layer in which the resin layer and the second resin layer are integrated; and a temperature change is applied to the joined body to separate the second substrate from the capacitor portion. And a separation step.

  The dielectric thin film capacitor manufacturing method of the present invention is characterized in that an adhesion layer is formed on the upper surface of the second substrate, and the capacitor portion is formed on the upper surface of the adhesion layer.

  Furthermore, the dielectric thin film capacitor manufacturing method of the present invention is characterized in that the thermal expansion coefficient of the second substrate is smaller than the thermal expansion coefficient of the first substrate.

  The dielectric thin film capacitor manufacturing method of the present invention is characterized in that the first substrate has a conductive via.

According to the dielectric thin film capacitor manufacturing method, the second electrode film, the dielectric thin film, and the first electrode film are sequentially formed on the second substrate having a thermal expansion coefficient different from that of the first substrate. Forming a capacitor portion and further forming a first resin layer so as to cover the capacitor portion on the second substrate, while forming a second resin layer made of the same material as the first resin layer. Formed on the surface of one substrate, the second substrate and the first substrate are overlapped so that the first resin layer and the second resin layer are in contact with each other; A joined body having an insulating layer integrated with the second resin layer is formed, and a temperature change is applied to the joined body to separate the second substrate from the capacitor portion. Even when 2 substrates are used, heating temperature, cooling temperature, and temperature change rate are selected appropriately The Rukoto, without the first and second substrate and the capacitor unit is damaged, it is possible to easily separate the second substrate and the capacitor section.

  In addition, as described above, the second substrate can be separated from the capacitor portion without being damaged, so that the second substrate can be reused, thereby saving resources and reducing production costs. Can be planned.

  In addition, since the adhesion layer is formed on the upper surface of the second substrate and the capacitor portion is formed on the upper surface of the adhesion layer, the adhesion between the second substrate and the dielectric thin film can be kept good, The second electrode film can be easily patterned on the dielectric thin film.

  In addition, since the thermal expansion coefficient of the second substrate is smaller than the thermal expansion coefficient of the first substrate, by applying a temperature change to the joined body, the second substrate and the second electrode film Interfacial peeling occurs easily between the second substrate and the second substrate and the capacitor portion can be easily separated. That is, since the thermal expansion coefficient of the second substrate is smaller than the thermal expansion coefficient of the first substrate, and the thermal expansion coefficients of the first and second electrode films and the dielectric thin film are relatively large, the capacitor Tensile stress is generated in the in-plane direction of the part. When a temperature change due to heating / cooling is applied to the joined body, the joined body is warped with the second substrate side having a relatively small coefficient of thermal expansion being convex due to thermal stress. On the side, tensile stress is generated in the peeling direction. That is, when the bonded body is heated and cooled, interface peeling occurs between the second substrate having the weakest adhesion strength and the second electrode film, and the second substrate and the capacitor portion can be easily separated. it can.

  In addition, since the first substrate has conductive vias, the capacitor portion can be electrically connected to the first substrate, and can be electrically connected to external electronic components such as LSI and other printed circuit boards. It becomes possible to connect.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view schematically showing one embodiment (first embodiment) of a dielectric thin film capacitor manufactured by the manufacturing method of the present invention.

  That is, upper electrodes 3a and 3b and lower electrodes 4a and 4b are formed on the upper and lower surfaces of the ceramic substrate (first substrate) 2 on which the conductive vias 1a and 1b are formed so as to cover the conductive vias 1a and 1b. ing. In addition, an insulating layer 5 is formed on the upper surface of the ceramic substrate 2, and a first conductive film 6 and a first electrode film 7 are formed so that the upper surface is flush with the insulating layer 5. A dielectric thin film 8 is formed on the upper surfaces of the layer 5 and the first electrode film 7. Then, a second electrode film 9 and a second conductive film 10 are formed on the surface of the dielectric thin film 8, and the capacitor unit 11 is formed by the first electrode film 7, the dielectric thin film 8 and the second electrode film 9. Forming.

  Further, a first conductive portion 12a having a substantially concave cross section is formed on the first conductive via 1a, and the second electrode film 9 and the second conductive film 10 are connected to the first conductive portion 12a via the first conductive portion 12a. The first conductive via 1 a is electrically connected to the first conductive via 1 a and is electrically insulated from the first electrode film 7 and the first conductive film 6.

  A second conductive portion 12b having a substantially concave cross section is also formed on the second conductive via 1b, and the first electrode film 7 and the first conductive film 6 are connected to each other via the second conductive portion 12b. The second conductive via 1 b is electrically connected to the second conductive via 1 b and electrically insulated from the second electrode film 9 and the second conductive film 10.

  A protective film 13 is formed so as to cover the second conductive film 10 and the first and second conductive portions 12a and 12b.

  Next, a method for manufacturing the dielectric thin film capacitor will be described in detail with reference to FIGS.

  First, as shown in FIG. 2 (a), an oxide layer 15, an adhesion layer 16, a second electrode film 9, a dielectric thin film 8, and an upper surface of a smooth Si substrate (second substrate) 14; The first electrode film 7 is sequentially formed.

That is, for example, a silicon single crystal substrate (hereinafter, simply referred to as “Si substrate”) 14 having a thickness of 525 μm and a linear expansion coefficient of 2.6 × 10 ⁻⁶ / K is subjected to a thermal oxidation treatment to obtain a film thickness of 0.7 μm. An oxide layer 15 made of SiO ₂ is formed, and then a 50 nm-thick adhesion layer 16 made of TiO ₂ is formed on the upper surface of the oxide layer 15 using a sputtering method. The adhesion layer 16 may be formed by sputtering, MOCVD (Metal Organic Chemical Vapor Deposition), vacuum deposition, MOD (Metal Organic Decomposition), etc. The film may be formed by other thin film forming methods. In the present embodiment, the adhesion layer 16 is formed of TiO ₂ , but Al ₂ O ₃ , TaO ₂ , ZnO, Ti—Si—O-based oxide, Al—Si—O-based oxide, Ta It can also be formed of -Si-O-based oxide, Zn-Si-O-based oxide, or the like.

  Next, a second electrode film 9 made of Pt having a thickness of 200 nm is formed on the surface of the adhesion layer 16 by using a thin film forming method such as a sputtering method. The film forming material of the second electrode film 9 is not limited to Pt as long as it is a noble metal material having good oxidation resistance even when exposed to a high temperature atmosphere. For example, Pd, Au, Ir , Ru, Rh, etc. can be used.

  Next, a film forming raw material in which Ba, Sr, and Ti are mixed at a molar ratio of, for example, Ba: Sr: Ti = 7: 3: 10 is prepared, and the surface of the second electrode film 9 is formed using the MOD method. A dielectric thin film 8 made of BST and having a thickness of 150 nm is formed. That is, for example, after spin coating and drying of the MOD raw material solution are repeated twice, rapid thermal annealing (hereinafter referred to as “RTA”) is performed in an oxygen atmosphere at a temperature of 650 ° C. for 30 minutes. A dielectric thin film 8 is formed on the surface of the second electrode film 9. The method for forming the dielectric thin film 8 is not limited to the MOD method, and the film can be formed by using a method such as MOCVD or sputtering.

  Next, a first electrode film 7 made of Pt with a thickness of 200 nm is formed on the upper surface of the dielectric thin film 8 by sputtering or the like, and further RTA is performed in this state in an oxygen atmosphere at a temperature of 800 ° C. for 30 minutes. Thus, by exposing to a high temperature atmosphere after film formation, a dielectric thin film 8 having a high dielectric constant can be obtained.

  Next, as shown in FIG. 2B, a Ti film 17, a Cu film 18, and a Ti film 19 having a predetermined pattern are formed by a lift-off method. That is, a photoresist is applied to the surface of the first electrode film 7 and then pre-baked, followed by exposure and development through a photomask, and then using a vacuum deposition method to form a Ti layer having a thickness of 50 nm, A 3 μm Cu layer and a 100 nm thick Ti layer are sequentially formed, and the photoresist and the conductive film on the photoresist, that is, the Ti layer, the Cu layer, and the Ti layer are removed, and a Ti film 17 having a predetermined pattern, A Cu film 18 and a Ti film 19 are formed. The first conductive film 6 is formed by the Ti film 17, the Cu film 18, and the Ti film 19. In the present embodiment, the first conductive film 6 is formed by a vacuum evaporation method, but may be formed by a sputtering method.

  Next, using the ion milling method with the Ti film 19 as a mask, the first electrode film 7 exposed on the surface is removed as shown in FIG. Since Pt constituting the first electrode film 7 has a higher milling speed than Ti and BST, the first electrode film 7 exposed on the surface can be selectively removed.

  Next, a heat-resistant resin, for example, a heat-resistant resin varnish having a glass transition point of about 250 ° C., is spin-coated, and further heat-treated in a nitrogen atmosphere at a temperature of 300 ° C. for 1 hour. Then, the first resin layer 20 is formed. Note that the thickness of the first resin layer 20 is controlled to be about 5 μm from the upper surface of the Cu film 18, for example.

On the other hand, as shown in FIG. 3E, a known ceramic substrate manufacturing technique is used to form a 500 μm thick ceramic substrate (linear expansion coefficient 8.0 × 10 ⁻⁶ / K) on which conductive vias 1a and 1b are formed. 2) is produced. That is, for example, after slurrying a low-temperature fired ceramic material containing crystallized glass or ceramic powder, a ceramic green sheet is produced using a molding method such as a doctor blade method, and then a laser processing machine is used. Drilling a via hole at a predetermined position of the ceramic green sheet, filling the via hole with a conductive paste, and then laminating a predetermined number of this ceramic green sheet to form a laminate, followed by firing treatment, Thereby, the ceramic substrate 2 on which the conductive vias 1a and 1b are formed is manufactured.

  Here, the conductive paste filled in the via hole is not particularly limited, but Pt and Au are mainly composed of Ag widely used in the conductive paste of the low-temperature sintered ceramic substrate. It is inexpensive and preferable.

  The ceramic material constituting the ceramic substrate 2 is not limited to the low-temperature fired ceramic material, and any ceramic material or resin multilayer substrate can be used, but the linear expansion coefficient is higher than that of the Si substrate 14. It needs to be big.

  Next, as shown in FIG. 3F, Ti films 21a and 21b and Cu films 22a and 22b are formed by a lift-off method so as to cover the exposed surfaces of the conductive vias 1a and 1b, whereby the upper electrode 3a, 3b is formed. That is, after a photoresist is applied on the upper surface of the ceramic substrate 2 and prebaked, exposure and development are performed through a photomask, and then a 50 nm-thick Ti layer and a 2 μm-thick Cu layer are formed using a vacuum deposition method. Are sequentially formed. Thereafter, the photoresist and the Ti layer and Cu layer on the photoresist are removed, and Ti films 21a and 21b and Cu films 22a and 22b are formed so as to cover the exposed surfaces of the conductive vias 1a and 1b. Electrodes 3a and 3b are formed.

  Similarly, the lift-off method is applied to the lower surface of the ceramic substrate 2 to form 50 nm thick Ti films 23a and 23b and 2 μm thick Cu films 24a and 24b so as to cover the exposed surfaces of the conductive vias 1a and 1b. Thus, the lower electrodes 4a and 4b are formed.

  Next, the heat-resistant resin varnish used for the production of the first resin layer 20 is spin-coated on the ceramic substrate 2 and further heat-treated in a nitrogen atmosphere at a temperature of 300 ° C. for 1 hour, as shown in FIG. In this way, the second resin layer 25 is formed. The thickness of the second resin layer 25 is controlled to be, for example, about 5 μm from the upper surface of the Cu films 22a and 22b.

Next, as shown in FIG. 4 (h), the first resin layer 20 and the second resin layer 25 are overlapped while being aligned, and heated at a temperature of 280 ° C. for 30 minutes under a pressure of 0.5 MPa. A pressure treatment is performed, and the Si substrate 14 and the ceramic substrate 2 are pressure-bonded, whereby the joined body 70 is produced. The first resin layer 20 and the second resin layer 25 constitute the insulating layer 5.

Next, the bonded body 70 is placed on a hot plate heated to 100 ° C. and held for 1 minute, and then immersed in water having a water temperature of 20 ° C., and the bonded body 26 is heated again to 100 ° C. Place on top. As a result, as shown in FIG. 4I, interfacial peeling occurs between the second electrode film 9 and the adhesion layer 16, and the Si substrate 14 and the ceramic substrate 2 are separated.

That is, the Si substrate 14 has a small linear expansion coefficient of 2.6 × 10 ⁻⁶ / K, and the first and second electrode films 7 and 9 and the dielectric thin film 8 are larger than the linear expansion coefficient of the Si substrate 14. Therefore, a tensile stress is generated in the in-plane direction of the second electrode film 9. In addition, the insulating layer 5 (first and second resin layers 20 and 25) and the ceramic substrate 2 also have a larger coefficient of linear expansion than the Si substrate 14, and therefore the bonded body 26 has a thermal stress after heating and cooling. As a result, the Si substrate 14 side is convex and warped, and tensile stress is generated in the peeling direction on the ceramic substrate 2 side. As a result, in the bonded body 26, interfacial peeling occurs between the adhesion layer 16 having the weakest adhesion strength and the second electrode film 9, and the Si substrate 14 and the ceramic substrate 2 are separated.

  In this embodiment, the heating / cooling process is performed twice, but the heating / cooling process may be repeated three or more times.

Further, the heating temperature, the cooling temperature, and the heating / cooling rate can be selected as long as the Si substrate 14 and the capacitor unit 11 are not damaged. Incidentally, when the joined body 70 was immersed in water having a water temperature of 20 ° C. after being heated to 210 ° C., the capacitor part 11 could be transferred onto the ceramic substrate 2, but the Si substrate 14 was split into two. For this reason, the Si substrate 14 can no longer be reused. However, when a Si substrate having a thickness of 300 μm is used, the Si substrate can be immersed in water having a water temperature of 20 ° C. even when the joined body 70 is heated to 250 ° C. 14 was not damaged. Therefore, it is preferable to select the heating temperature, the cooling temperature, and the heating / cooling rate within a range in which the Si substrate 14 is not damaged in consideration of the thickness of the Si substrate 14.

  Next, after cleaning and drying the ceramic substrate 2 to which the capacitor portion 11 has been transferred, the lift-off method described above is used, and as shown in FIG. A Cu film 27 having a thickness of 3 μm and a Ti film 28 having a thickness of 100 nm are formed. The Ti film 26, the Cu film 27, and the Ti film 28 constitute the second conductive film 10.

  Next, using the ion milling method with the Ti film 28 as a mask, the second electrode film 9 exposed on the surface is removed as shown in FIG. 5 (k), as in FIG. 2 (c).

  Next, as shown in FIG. 5L, a photoresist 29 is applied on the upper surfaces of the second conductive film 10 and the dielectric thin film 8.

  Next, as shown in FIG. 5M, first and second holes 30a and 30b are formed by a well-known photolithography technique and reactive ion etching, and the upper electrodes 3a and 3b are exposed on the surface. That is, after pre-baking the photoresist 29, the photoresist 29 is irradiated with ultraviolet light through a photomask, exposed, developed, and post-baked to transfer the photomask pattern to the resist pattern, and an ICP-RIE apparatus (Inductively -Coupled Plasma Reactive Ion Etching: Inductively coupled plasma reactive ion etching) is used to form first and second holes 30a, 30b, and the upper electrodes 3a, 3b are exposed on the surface.

  Next, as shown in FIG. 6 (n), the photoresist 29 is dissolved and removed.

  Next, the lift-off method described above is used again to form 50 nm thick Ti films 31 a and 32 a and 5 μm thick Cu films 31 b and 32 b each having a predetermined pattern, as shown in FIG. The Ti film 31a and the Cu film 31a constitute the first conductive part 12a, and the Ti film 31b and the Cu film 31b constitute the second conductive part 12b.

  Next, after applying a heat-resistant resin varnish, heat treatment is performed in a nitrogen atmosphere at a temperature of 300 ° C. for 1 hour to form a protective film 13 as shown in FIG. 6 (p), whereby a dielectric thin film capacitor is manufactured. The

  As described above, in the first embodiment, the capacitor unit 11 is formed on the Si substrate 14 having a small linear expansion coefficient, and the Si substrate 14 on which the capacitor unit 11 is formed is connected to the capacitor unit 11 side, the ceramic substrate 2, and the like. Are joined and bonded together to form a joined body 26, and then a temperature change is applied to the joined body 26, so that the Si substrate 14, the ceramic substrate 2, and the capacitor portion 11 are not damaged. The Si substrate 14 can be separated from the capacitor unit 11.

  Therefore, even when the capacitor unit 11 is formed on the large Si substrate 14, the Si substrate 14 can be quickly separated from the capacitor unit 11, and productivity can be improved.

  Moreover, since the Si substrate 14 is not damaged as described above, it can be reused, and resource saving and production cost reduction can be achieved. That is, in this case, the adhesion layer 16 remains on the surface of the Si substrate 14, but when the surface state of the adhesion layer 16 does not change greatly and is sufficiently smooth, it is reused as it is as the Si substrate 14 with the adhesion layer 16. can do. When the adhesion layer 16 has lost smoothness and adhesion, the adhesion layer can be selectively dissolved and removed using an etching solution such as an aqueous tetramethylammonium hydroxide solution that does not dissolve the oxide layer 15. As a result, the Si substrate 14 with the oxide layer 15 is obtained and can be reused.

  7 to 9 are manufacturing process diagrams showing a second embodiment of the method of manufacturing a dielectric thin film capacitor. In the second embodiment, an adhesion layer is not formed on the Si substrate 14. The capacitor part 33 is formed directly.

That is, first, as shown in FIG. 7A, thermal oxidation is performed on the Si substrate 14 to form an oxide layer (SiO ₂ layer) 15, and thereafter, the same method as in the first embodiment, The second electrode film 34, the dielectric thin film 35, the first electrode film 36, the Ti film 38, the Cu film 39, the Ti film 40, and the One resin layer 41 is sequentially formed.

  Next, as shown in FIG. 7B, the ceramic substrate 2 having the second resin layer 25 formed on the surface and the Si substrate 14 are overlapped so that the resin surfaces are bonded to each other, and the pressure is 0.5 MPa. Then, a heat and pressure treatment is performed at a temperature of 280 ° C. for 30 minutes, and the Si substrate 14 and the ceramic substrate 2 are pressure-bonded, whereby the joined body 60 is manufactured.

  In the second embodiment, since the adhesion layer is not provided on the Si substrate 14, the adhesion between the Si substrate 14 and the second electrode film 34 or the dielectric thin film 35 is poor. Therefore, since there is a possibility that the patterning of the first electrode film 36 cannot be performed successfully, the first electrode film 36 and the first conductive film 37 are formed over the entire upper surface of the dielectric film 35, and in this state The joined body 60 is produced.

  After that, as in the first embodiment, the joined body 60 is subjected to predetermined heating / cooling treatment, whereby the oxide layer 15 and the first electrode film 36 are formed as shown in FIG. Interfacial peeling occurs between the Si substrate 14 and the ceramic substrate 2.

  Next, as shown in FIG. 8D, similarly to the first embodiment, a Ti film 43, a Cu film 44, and a Ti film to be the second conductive film 42 are formed by using the vapor deposition lift-off method. 45 is sequentially formed, and then the second electrode film 36 exposed on the surface is removed by an ion milling method, and then a photoresist 46 is applied to the surface.

  Next, the above-described well-known photolithography technique and reactive ion etching are performed to form first and second holes 47a and 47b to expose the upper electrodes 3a and 3b as shown in FIG. 8E. Further, the photoresist 46 is dissolved and removed.

Next, a film forming process is performed at a temperature of 200 ° C. by a plasma CVD method using tetraethoxysilane as a raw material to form an insulating layer 48 made of SiO ₂ having a thickness of 0.5 μm as shown in FIG. The insulating layer 48 can be formed even at room temperature.

  Next, the above-described photolithography technique is used again to remove the insulating layer 48 in a region excluding the inside of the first hole 47a, and the patterned insulating layer 48 is formed. After this, the photoresist on the insulating layer 48 is dissolved and removed. FIG. 9G shows the state after the photoresist is dissolved and removed.

  Next, using the above-described lift-off method, as shown in FIG. 9 (h), a first conductive portion 51a composed of a Ti film 49a and a Cu film 50a above the upper electrodes 3a and 3b, a Ti film 49b, A second conductive portion 51b made of the Cu film 50b is formed.

  Next, after applying a heat-resistant resin varnish, a heat treatment is performed in a nitrogen atmosphere at a temperature of 300 ° C. for 1 hour to form a protective film 52 as shown in FIG. 9 (i), whereby a dielectric thin film capacitor is manufactured. The

  Thus, unlike the first embodiment, the second embodiment has no adhesion layer between the oxide layer 15 and the second conductive film 34, but the first embodiment. Similarly to the above, by applying a temperature change to the bonded body 60, the capacitor part 33 can be separated from the Si substrate 14 without damaging the Si substrate 14, the ceramic substrate 2, and the capacitor part 33.

  Therefore, even when the capacitor portion 33 is formed on the large Si substrate 14, the Si substrate 14 can be quickly separated from the capacitor portion 33, and productivity can be improved.

  In addition, since the Si substrate 14 is not damaged in this way, it can be reused, saving resources and reducing costs.

  FIG. 10 is a diagram showing the main part of the third embodiment of the manufacturing method. In the third embodiment, the second electrode film 55 formed on the adhesion layer 16 is made of Au. A two-layer structure of a film 53 and a Pt film 54 is employed.

  That is, in the third embodiment, after the oxide layer 15 and the adhesion layer 16 are sequentially formed on the Si substrate 14 as in the first embodiment, an appropriate peeling is performed by a thin film forming method such as a sputtering method. The Au thin film 53 and the Pt film 54 that effectively contribute to improving the characteristics of the dielectric thin film 8 are sequentially formed, and the dielectric thin film 8 and the first electrode film 7 are sequentially formed on the Pt film 54. .

  Then, as shown in FIG. 11 (a), the ceramic substrate 2 and the Si substrate 14 are joined to produce a joined body 61, and thereafter, a temperature change is applied to the joined body 61 as in the first embodiment. As a result, interfacial peeling occurs between the Au film 53 having an appropriate peelability and the adhesion layer 16, and the Si substrate 14 and the ceramic substrate 2 can be separated as shown in FIG.

  In this way, it is also preferable to form a metal film having appropriate peelability on the Si substrate 14 side and to form a metal film that effectively contributes to improving the characteristics of the dielectric thin film 8 on the dielectric thin film 8 side.

  The present invention is not limited to the above-described embodiment. In the above-described embodiment, the case where the capacitor unit 11 has a single layer structure has been described. However, the present invention can also be applied to a case where the capacitor unit has a multilayer structure. Needless to say. That is, a film formation process is repeatedly performed on the first electrode film 7 formed on the Si substrate 14 in the order of dielectric thin film → second electrode film → dielectric thin film → first electrode film →. The part 11 may have a multilayer structure.

  In addition, the film thickness of each thin film shown in the above embodiment is merely an example, and it goes without saying that it can be arbitrarily set within a range in which the size and weight can be maintained and the function as a dielectric thin film capacitor is not impaired. .

It is sectional drawing which showed typically the dielectric thin film capacitor manufactured with the manufacturing method which concerns on the 1st Embodiment of this invention. It is a manufacturing process figure (1/5) which shows a 1st embodiment of a manufacturing method of a dielectric thin film capacitor concerning the present invention. It is a manufacturing process figure (2/5) which shows a 1st embodiment of a manufacturing method of a dielectric thin film capacitor concerning the present invention. It is a manufacturing process figure (3/5) which shows a 1st embodiment of a manufacturing method of a dielectric thin film capacitor concerning the present invention. It is a manufacturing process figure (4/5) which shows 1st Embodiment of the manufacturing method of the dielectric thin film capacitor which concerns on this invention. It is a manufacturing process figure (5/5) which shows 1st Embodiment of the manufacturing method of the dielectric thin film capacitor which concerns on this invention. It is a manufacturing-process figure (1/3) which shows 2nd Embodiment of the manufacturing method of the dielectric thin film capacitor of this invention. It is a manufacturing process figure (2/3) which shows 2nd Embodiment of the manufacturing method of the dielectric thin film capacitor of this invention. It is a manufacturing process figure (3/3) which shows 2nd Embodiment of the manufacturing method of the dielectric thin film capacitor of this invention. It is principal part manufacturing process drawing (1/2) which shows 3rd Embodiment of the manufacturing method of the dielectric thin film capacitor of this invention. It is principal part manufacturing process drawing (2/2) which shows 3rd Embodiment of the manufacturing method of the dielectric thin film capacitor of this invention. It is a manufacturing process figure which shows the manufacturing method of the electronic circuit with a built-in capacitor | condenser disclosed by patent document 1. FIG.

Explanation of symbols

2 Ceramic substrate (first substrate)
7 First electrode film 8 Dielectric thin film 9 Second electrode film 11 Capacitor part 14 Si substrate (second substrate)
16 Adhesive layer 26 Bonded body 33 Capacitor part 34 Second electrode film 35 Dielectric thin film 36 First electrode film 60 Bonded body 61 Bonded body

Claims (4)

A method of manufacturing a dielectric thin film capacitor, wherein a capacitor portion in which a first electrode film and a second electrode film are formed to face each other via a dielectric thin film is formed on a first substrate,
Capacitor formation for sequentially forming the second electrode film, the dielectric thin film, and the first electrode film on a second substrate having a coefficient of thermal expansion different from that of the first substrate to form a capacitor portion Process,
A first resin layer forming step of forming a first resin layer so as to cover the capacitor portion on the second substrate;
A second resin layer forming step of forming a second resin layer made of the same material as the first resin layer on the surface of the first substrate;
The second substrate and the first substrate are overlapped so that the first resin layer and the second resin layer are in contact with each other, and the first resin layer and the second resin layer are integrated. A joined body forming step of forming a joined body having an insulating layer,
A separation step of separating the second substrate from the capacitor portion on the second substrate by applying a temperature change to the joined body;
A method for manufacturing a dielectric thin film capacitor, comprising:   2. The method of manufacturing a dielectric thin film capacitor according to claim 1, wherein an adhesion layer is formed on the upper surface of the second substrate, and the capacitor portion is formed on the upper surface of the adhesion layer.   3. The method of manufacturing a dielectric thin film capacitor according to claim 1, wherein a thermal expansion coefficient of the second substrate is smaller than a thermal expansion coefficient of the first substrate.   4. The method of manufacturing a dielectric thin film capacitor according to claim 1, wherein the first substrate has a conductive via.

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