JPS622465B2 - - Google Patents

Info

Publication number
JPS622465B2
JPS622465B2 JP55141717A JP14171780A JPS622465B2 JP S622465 B2 JPS622465 B2 JP S622465B2 JP 55141717 A JP55141717 A JP 55141717A JP 14171780 A JP14171780 A JP 14171780A JP S622465 B2 JPS622465 B2 JP S622465B2
Authority
JP
Japan
Prior art keywords
film
single crystal
crystal silicon
region
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55141717A
Other languages
English (en)
Other versions
JPS5766674A (en
Inventor
Minoru Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55141717A priority Critical patent/JPS5766674A/ja
Priority to US06/304,913 priority patent/US4420870A/en
Publication of JPS5766674A publication Critical patent/JPS5766674A/ja
Publication of JPS622465B2 publication Critical patent/JPS622465B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特に電界効果トラ
ンジスターの構造に係わるものである。
近年、電界効果トランジスタ（MOS）集積回
路素子の微細化・高集積化が進んでおり、この結
果、実効チヤネル長の制御と共に、所期目的のチ
ヤンネル長より短かくなること（以下、チヤンネ
ル長のシヨート化と称す）をいかに防止するかが
大きな問題となつている。
このチヤンネルのシヨート化を防止するために
は、ゲート近傍のソース・ドレイン領域を形成す
る拡散層を浅くすれば良いが、このように浅い拡
散層は抵抗が高くなつて高速度化が妨げる欠点が
あつた。
本発明は、上記欠点を除去し、実効チヤネル長
の制御が容易で、しかもチヤネル長のシヨート化
を防止して高速度化を図つた半導体装置を提供す
ることを目的とするものである。
以下本発明を図面に示す実施例を参照して詳細
に説明する。
第１図乃至第７図は、MOSトランジスタに適
用した場合の本発明の一実施例を順次工程に従つ
て示すものである。
先ず第１図に示すように半導体基板として単結
晶シリコン基板１を用意し、この表面にフオレジ
ストを塗布した後、写真蝕刻法によりレジストパ
ターン２を形成し、次いで1014〜1016／cm2のシリ
コンを30〜60keVの加速電圧でイオン注入し、露
出した単結晶シリコン基板１の表面を粗くして結
晶性をなくす。
次にレジストパターン２を除去した後、エピタ
キシヤル成長を行ない、第２図に示すようにシリ
コンをイオン注入して結晶性をなくした領域に多
結晶シリコン膜３を成長させると共に、レジスト
パターン２で覆われていた領域に単結晶シリコン
膜４を成長させる。
この後、ドライ酸化により表面に約600Åのシ
リコン酸化膜５を形成し、更にこの上にシリコン
窒化膜６を厚さ約3000Åに堆積した後、このシリ
コン窒化膜６とシリコン酸化膜５とを順次選択的
にエツチング除去して、第３図に示すように素子
形成領域に耐酸化性マスクを形成する。
次にスチーム酸化を行なつて第４図に示すよう
に厚さ約8000Åのフイールド酸化膜７を形成した
後、耐酸化性マスクを除去する。
この後、ドライ酸化を行ない耐酸化性マスクを
除去した素子形成領域に、ゲート酸化膜となるシ
リコン酸化膜８を約500Åの厚さに形成し、次い
でこの上にCVD法により多結晶シリコン膜を厚
さ3000〜4000Åに堆積した後、単結晶シリコン膜
４の一部上面を残して多結晶シリコン膜を選択的
に除去して、第５図に示すようにゲート電極９を
形成する。
次にゲート電極９となる多結晶シリコン膜を保
護マスクとしてイオン注入により１〜３×1015／
cm2の砒素Asを50keVの加速電圧でドープし、ｎ+
型のソース領域１０及びドレイン領域１１を形成
し、第６図のように構成する。この場合、イオン
注入による砒素の拡散は、単結晶シリコン膜４に
比べて多結晶シリコン膜３では数倍の深さに進行
するため、ソース領域１０およびドレイン領域１
１は多結晶シリコン膜３から単結晶シリコン膜４
の界面を含むように延出し、しかも単結晶シリコ
ン膜４中での深さが浅く、横方向への拡散も少な
い状態となる。
次に第７図に示すように、通常の素子形成方法
に従つてCVD法により厚さ3000ÅのCVD−SiO2
膜１２、および厚さ8000ÅのBPSG（ボロン、リ
ン、シリケート、グラス）膜１３を順次堆積し、
更にコンタクトホール１４を明けてアルミニウム
蒸着、パターニングを経てソース電極１５および
ドレーン電極１６を形成して第７図に示す如き
MOSトランジスタを形成する。
従つて上記構成のMOSトランジスタはソース
領域１０およびドレイン領域１１が、ゲート電極
９の近傍のみ浅く形成され、ゲート電極９より離
れたところが深く形成されているので、実行チヤ
ネル長の制御が容易で、しかもチヤンネル長のシ
ヨート化を防止できると共に、拡散層の深さが十
分に深く抵抗も少なくすることがでるので高速度
化も達成することができる。
また単結晶シリコン基板１の上に多結晶シリコ
ン膜３を形成する方法として、単結晶シリコン基
板１の表面に熱酸化膜を形成した後、エピタキシ
ヤル成長させる方法もあるが、この場合熱酸化膜
が不純物拡散の絶縁膜となり十分な拡散深さが得
られない。しかしながら上記の如くシリコンをイ
オン注入して単結晶シリコン基板１の表面を粗く
して結晶性をなくした後、エピタキシヤル成長さ
せて多結晶シリコン膜３を形成する方法では、界
面に絶縁膜がないため十分な深さに拡散し、更に
抵抗の少ないソース領域１０とドレイン領域１１
を形成させることができる。
なお上記実施例では不純物として砒素をイオン
注入した場合について示したがボロンをイオン注
入しても良い。また上記実施例ではＮチヤンネル
トランジスタについて説明したがＰチヤンネルト
ランジスタでも良く、また相補型MOSトランジ
スタにも同様に適用することができる。
更にゲート構造は、シリサイドゲートやその他
のメタルゲートでも良く、また半導体基板に代え
てサフアイヤ等の絶縁性基板を用いることも可能
である。
以上説明した如く、本発明に係わる半導体装置
によれば、実行チヤネル長の制御が容易で、しか
もチヤンネル長のシヨート化を防止して、高速度
化を図ることができるなど顕著な効果を有するも
のである。
【図面の簡単な説明】
第１図乃至第７図は本発明の一実施例による
MOSトランジスタを製造する工程を順次示す断
面図である。 １……単結晶シリコン基板、２……レジストパ
ターン、３……多結晶シリコン膜、４……単結晶
シリコン膜、５……シリコン酸化膜、６……シリ
コン窒化膜、７……フイールド酸化膜、８……シ
リコン酸化膜、９……ゲート電極、１０……ソー
ス領域、１１……ドレイン領域。

Claims (1)

    【特許請求の範囲】
  1. １ 表面に単結晶領域と多結晶領域とを選択的に
    形成した半導体基板の、前記単結晶領域の一部上
    面にゲート電極を形成し、この両側に配置したソ
    ース・ドレイン領域が前記多結晶領域から延長し
    て単結晶領域との界面を含んで形成されたことを
    特徴とする半導体装置。
JP55141717A 1980-10-09 1980-10-09 Semiconductor device Granted JPS5766674A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP55141717A JPS5766674A (en) 1980-10-09 1980-10-09 Semiconductor device
US06/304,913 US4420870A (en) 1980-10-09 1981-09-23 Method of controlling channel length by implanting through polycrystalline and single crystalline regions followed by diffusion anneal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55141717A JPS5766674A (en) 1980-10-09 1980-10-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5766674A JPS5766674A (en) 1982-04-22
JPS622465B2 true JPS622465B2 (ja) 1987-01-20

Family

ID=15298553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55141717A Granted JPS5766674A (en) 1980-10-09 1980-10-09 Semiconductor device

Country Status (2)

Country Link
US (1) US4420870A (ja)
JP (1) JPS5766674A (ja)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599118A (en) * 1981-12-30 1986-07-08 Mostek Corporation Method of making MOSFET by multiple implantations followed by a diffusion step
USRE32800E (en) * 1981-12-30 1988-12-13 Sgs-Thomson Microelectronics, Inc. Method of making mosfet by multiple implantations followed by a diffusion step
US4459159A (en) * 1982-09-29 1984-07-10 Mara William C O Method for making semi-insulating substrate by post-process heating of oxygenated and doped silicon
US5242844A (en) * 1983-12-23 1993-09-07 Sony Corporation Semiconductor device with polycrystalline silicon active region and method of fabrication thereof
KR930007195B1 (ko) * 1984-05-23 1993-07-31 가부시끼가이샤 히다찌세이사꾸쇼 반도체 장치와 그 제조 방법
US5352620A (en) * 1984-05-23 1994-10-04 Hitachi, Ltd. Method of making semiconductor device with memory cells and peripheral transistors
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
DE3682021D1 (de) * 1985-10-23 1991-11-21 Hitachi Ltd Polysilizium-mos-transistor und verfahren zu seiner herstellung.
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US5923985A (en) * 1987-01-05 1999-07-13 Seiko Instruments Inc. MOS field effect transistor and its manufacturing method
US5289027A (en) * 1988-12-09 1994-02-22 Hughes Aircraft Company Ultrathin submicron MOSFET with intrinsic channel
JPH0637317A (ja) * 1990-04-11 1994-02-10 General Motors Corp <Gm> 薄膜トランジスタおよびその製造方法
US5521107A (en) * 1991-02-16 1996-05-28 Semiconductor Energy Laboratory Co., Ltd. Method for forming a field-effect transistor including anodic oxidation of the gate
EP0499979A3 (en) 1991-02-16 1993-06-09 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US5930608A (en) * 1992-02-21 1999-07-27 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor in which the channel region of the transistor consists of two portions of differing crystallinity
JP2845303B2 (ja) 1991-08-23 1999-01-13 株式会社 半導体エネルギー研究所 半導体装置とその作製方法
JPH05183159A (ja) * 1992-01-07 1993-07-23 Fujitsu Ltd 半導体装置及びその製造方法
US5501989A (en) * 1993-03-22 1996-03-26 Semiconductor Energy Laboratory Co., Ltd. Method of making semiconductor device/circuit having at least partially crystallized semiconductor layer
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
US5773328A (en) * 1995-02-28 1998-06-30 Sgs-Thomson Microelectronics, Inc. Method of making a fully-dielectric-isolated fet
US6482660B2 (en) 2001-03-19 2002-11-19 International Business Machines Corporation Effective channel length control using ion implant feed forward

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3472712A (en) * 1966-10-27 1969-10-14 Hughes Aircraft Co Field-effect device with insulated gate
DE2449688C3 (de) * 1974-10-18 1980-07-10 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines Leitfähigkeitstyps in einem Halbleiterkörper
US4167806A (en) * 1976-09-28 1979-09-18 Commissariat A L'energie Atomique Method of fabrication of an amorphous semiconductor device on a substrate
US4216573A (en) * 1978-05-08 1980-08-12 International Business Machines Corporation Three mask process for making field effect transistors

Also Published As

Publication number Publication date
US4420870A (en) 1983-12-20
JPS5766674A (en) 1982-04-22

Similar Documents

Publication Publication Date Title
JPS622465B2 (ja)
US6297132B1 (en) Process to control the lateral doping profile of an implanted channel region
KR100227766B1 (ko) 반도체 장치 및 그 제조 방법
US4711017A (en) Formation of buried diffusion devices
EP0055521B1 (en) Method of filling a groove in a semiconductor substrate
EP0091984B1 (en) Integrated circuit devices comprising dielectric isolation regions and methods for making such devices
US4532696A (en) Method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate
US4853342A (en) Method of manufacturing semiconductor integrated circuit device having transistor
US6171895B1 (en) Fabrication of buried channel devices with shallow junction depth
US4560421A (en) Semiconductor device and method of manufacturing the same
US5547903A (en) Method of elimination of junction punchthrough leakage via buried sidewall isolation
US4535529A (en) Method of making semiconductor devices by forming an impurity adjusted epitaxial layer over out diffused buried layers having different lateral conductivity types
JPS6355780B2 (ja)
JPS6362108B2 (ja)
US5340757A (en) Method of manufacturing a vertical field effect transistor
EP0126292A1 (en) Semiconductor device having an element isolation layer and method of manufacturing the same
JPH0324069B2 (ja)
JP2968078B2 (ja) Ｍｏｓトランジスタの製造方法
JPS6310896B2 (ja)
JP3060948B2 (ja) 半導体装置の製造方法
JPS6119111B2 (ja)
KR100347149B1 (ko) 반도체 장치 제조방법
JPH0491481A (ja) Ｍｉｓ電界効果トランジスタ
JPS628028B2 (ja)
JP2550728B2 (ja) 半導体装置の製造方法