JPS6224629A - 半導体表面保護膜形成方法 - Google Patents

半導体表面保護膜形成方法

Info

Publication number
JPS6224629A
JPS6224629A JP60163042A JP16304285A JPS6224629A JP S6224629 A JPS6224629 A JP S6224629A JP 60163042 A JP60163042 A JP 60163042A JP 16304285 A JP16304285 A JP 16304285A JP S6224629 A JPS6224629 A JP S6224629A
Authority
JP
Japan
Prior art keywords
protective film
group
surface protective
interface
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60163042A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0262943B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Toshitaka Torikai
俊敬 鳥飼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60163042A priority Critical patent/JPS6224629A/ja
Publication of JPS6224629A publication Critical patent/JPS6224629A/ja
Publication of JPH0262943B2 publication Critical patent/JPH0262943B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28264Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
JP60163042A 1985-07-25 1985-07-25 半導体表面保護膜形成方法 Granted JPS6224629A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60163042A JPS6224629A (ja) 1985-07-25 1985-07-25 半導体表面保護膜形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60163042A JPS6224629A (ja) 1985-07-25 1985-07-25 半導体表面保護膜形成方法

Publications (2)

Publication Number Publication Date
JPS6224629A true JPS6224629A (ja) 1987-02-02
JPH0262943B2 JPH0262943B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-12-27

Family

ID=15766077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60163042A Granted JPS6224629A (ja) 1985-07-25 1985-07-25 半導体表面保護膜形成方法

Country Status (1)

Country Link
JP (1) JPS6224629A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005022624A1 (ja) * 2003-08-28 2007-11-01 国立大学法人東京農工大学 絶縁膜形成方法
JP2009260325A (ja) * 2008-03-26 2009-11-05 Univ Of Tokyo 半導体基板、半導体基板の製造方法および半導体装置
JP2013012675A (ja) * 2011-06-30 2013-01-17 Canon Anelva Corp 金属酸化物高誘電体エピタキシャル膜の製造方法、および基板処理装置
JP2014220364A (ja) * 2013-05-08 2014-11-20 株式会社豊田自動織機 半導体基板の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005022624A1 (ja) * 2003-08-28 2007-11-01 国立大学法人東京農工大学 絶縁膜形成方法
JP2009260325A (ja) * 2008-03-26 2009-11-05 Univ Of Tokyo 半導体基板、半導体基板の製造方法および半導体装置
CN101978503A (zh) * 2008-03-26 2011-02-16 国立大学法人东京大学 半导体基板、半导体基板的制造方法及半导体装置
JP2013012675A (ja) * 2011-06-30 2013-01-17 Canon Anelva Corp 金属酸化物高誘電体エピタキシャル膜の製造方法、および基板処理装置
JP2014220364A (ja) * 2013-05-08 2014-11-20 株式会社豊田自動織機 半導体基板の製造方法

Also Published As

Publication number Publication date
JPH0262943B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-12-27

Similar Documents

Publication Publication Date Title
KR900003830B1 (ko) 실리콘판 또는 이산화실리콘판의 접착방법
US6168659B1 (en) Method of forming gallium nitride crystal
US5933705A (en) Passivation and protection of semiconductor surface
JP4954853B2 (ja) 2つの固体材料の分子接着界面における結晶欠陥および/または応力場の顕在化プロセス
Konaka et al. A new silicon‐on‐insulator structure using a silicon molecular beam epitaxial growth on porous silicon
JPH02290045A (ja) 非珪素半導体層を絶縁層に形成する方法
JPH01270593A (ja) 化合物半導体層形成方法
US6025281A (en) Passivation of oxide-compound semiconductor interfaces
US4843037A (en) Passivation of indium gallium arsenide surfaces
JPS6224629A (ja) 半導体表面保護膜形成方法
JP3602443B2 (ja) 半導体素子の製法
JP3245136B2 (ja) 絶縁膜の膜質改善方法
Berkovits et al. Nitride chemical passivation of a GaAs (100) Surface: Effect on the electrical characteristics of Au/GaAs surface-barrier structures
EP0562273A2 (en) Method for improving the interface characteristics of CaF2 on silicon
JPS6128213B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0797567B2 (ja) 薄膜の形成方法
JPS58170069A (ja) 3−v族化合物半導体装置
JPS5847875B2 (ja) 発光ダイオ−ド用ウエ−ハ
JPS6223453B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
Shibayama et al. Shrinkage effect of stacking faults during HCl oxidation in steam
Yokoyama et al. GaAs MOS structures with Al2O3 grown by molecular beam reaction
JPH021123A (ja) 分離酸化中シールされる界面のためのオキシナイトライドを形成する急速熱窒化方法
US5175129A (en) Method of fabricating a semiconductor structure having an improved polysilicon layer
JP2706964B2 (ja) 半導体装置の製造方法
JPS6235539A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term