JPS62245657A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62245657A JPS62245657A JP61089410A JP8941086A JPS62245657A JP S62245657 A JPS62245657 A JP S62245657A JP 61089410 A JP61089410 A JP 61089410A JP 8941086 A JP8941086 A JP 8941086A JP S62245657 A JPS62245657 A JP S62245657A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor substrate
- contact hole
- forming
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010410 layer Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 230000004224 protection Effects 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000009795 derivation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的コ □゛□
□
（産業上の利用分野）
この発明は、ＣＭＯＳ構造を有する半導体装置の製造方
法に関するもので、特に高密度集積回路の配線に使用さ
れるものである。[Detailed Description of the Invention] [Purpose of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device having a CMOS structure, and in particular to a method for manufacturing a semiconductor device having a CMOS structure. It is something that
（従来の技術）
従来、ＣＭＯＳ構造の半導体装置は、例えば第２図（ａ
）〜（Ｃ）に示すような工程で形成される。第２図は、
Ｎチャネル型のＭＯＳ ＦＥＴとＰチャネル型のＭＯ
Ｓ ＦＥＴのソース、ドレイン電極の導出に着目して
示しており、まず、Ｎ型の半導体（シリコン）基板１１
にＰ型のウェル領域１２を形成した後、素子分離用のフ
ィールド酸化膜１３１〜１３３を形成する。次に、上記
半導体基板１１上に薄い酸化膜を介してポリシリコン層
を形成し、パターニングを行なってゲート電極１４．１
５を形成する。そして、これらゲート電極１４．１５を
マスクにして不純物のイオン注入を行なうことにより、
上記半導体基板１１の表面領域内にはＰ＋型の不純物拡
散層〈Ｐチャネル型ＭＯ８ＦＥＴのソース、ドレイン領
域） １６ａ 、 １６ｂを、上記ウェル領域１２の表
面領域に内にはＮ＋型の不純物拡散層（Ｎチャネル型Ｍ
Ｏ８ＦＥＴのソース、ドレイン領域） １７ａ 、 １
７ｂをそれぞれ形成する。このようにしてＰチャネル型
およびＮチャネル型のＭＯＳ ＦＥＴを形成した半導
体基体上に、ＣＶＤ−８ｉＯ２膜１８を堆積形成し、こ
のＣＶＤ・５ｉ０２膜１８上にＢＰＳＧ膜１９膜剤９い
はＰＳＧ膜）を形成する。次に、上記Ｎチャネル型のＭ
ＯＳ ＦＥＴのソース、ドレイン領域としてのＮ＋型
型数散層１７ａ １７ｂ上のＣＶＤ−８ｉＯ２膜１８お
よびＢＰＳＧ膜１９膜剤９タクトホール２０ａ。(Prior Art) Conventionally, a semiconductor device having a CMOS structure is shown in FIG.
) to (C). Figure 2 shows
N-channel type MOS FET and P-channel type MO
The drawing focuses on the derivation of the source and drain electrodes of the S FET. First, the N-type semiconductor (silicon) substrate 11 is
After forming a P-type well region 12, field oxide films 131 to 133 for element isolation are formed. Next, a polysilicon layer is formed on the semiconductor substrate 11 via a thin oxide film, and patterned to form a gate electrode 14.1.
form 5. Then, by implanting impurity ions using these gate electrodes 14 and 15 as a mask,
In the surface region of the semiconductor substrate 11, there are P+ type impurity diffusion layers (source and drain regions of P channel type MO8FET) 16a and 16b, and in the surface region of the well region 12, there are N+ type impurity diffusion layers ( N-channel type M
Source and drain regions of O8FET) 17a, 1
7b respectively. A CVD-8iO2 film 18 is deposited on the semiconductor substrate on which P-channel and N-channel MOS FETs are formed in this way, and a BPSG film 19 or a PSG film is deposited on this CVD-5i02 film 18. ) to form. Next, the above N-channel type M
CVD-8iO2 film 18 and BPSG film 19 film agent 9 tact hole 20a on N+ type scattering layer 17a and 17b as source and drain regions of OS FET.
２０ｂを開孔し、これらのコンタクトホール２０ａ。20b and these contact holes 20a.
２０ｂ内に選択エピタキシャル成長法によりＮ＋型のシ
リコン層２１ａ、 ２１ｂを成長形成する。N+ type silicon layers 21a and 21b are grown in 20b by selective epitaxial growth.
次に、熱酸化を行なって、（ｂ）図に示すように上記シ
リコン層２１ａ、２１ｂの表面に酸化膜２２ａ。Next, thermal oxidation is performed to form an oxide film 22a on the surfaces of the silicon layers 21a and 21b, as shown in FIG.
２２ｂを形成する。そして、この酸化膜２２ａ、２２ｂ
によって上記シリコン層２１ａ、２１ｂを保護しつつコ
ンタクトホール２３ａ、２３ｂを開孔する。22b is formed. Then, these oxide films 22a, 22b
Contact holes 23a and 23b are opened while protecting the silicon layers 21a and 21b.
次に、（Ｃ）図に示すように、上記コンタクトホール２
３ａ、 ２３ｂ内に選択エピタキシャル成長法によりＰ
＋型のシリコン層２４ａ、２４ｂを成長形成し、上記酸
化膜２２ａ、２２ｂを除去した後、スパッタ法により半
導体基体上にアルミニウム層を形成し、このアルミニウ
ム層をパターニングして配線２５ａ〜２５ｄを形成する
。Next, as shown in Figure (C), the contact hole 2 is
3a and 23b by selective epitaxial growth.
After growing +-type silicon layers 24a and 24b and removing the oxide films 22a and 22b, an aluminum layer is formed on the semiconductor substrate by sputtering, and this aluminum layer is patterned to form interconnections 25a to 25d. do.
しかし、上述した製造方法では、Ｐチャネル型のＭＯＳ
ＦＥＴのコンタクトホール２３ａ、２３ｂ内にシリ
コン層２４ａ、２４ｂを成長形成した後、Ｎチャネル型
のＭＯＳ ＦＥＴ側の酸化膜２２ａ。However, in the above manufacturing method, P-channel type MOS
After silicon layers 24a and 24b are grown in contact holes 23a and 23b of the FET, an oxide film 22a is grown on the N-channel MOS FET side.
２２ｂをエツチングにより除去したが、このエツチング
時にＢＰＳＧ膜１９膜剤９れ（酸化膜２２ａ。22b was removed by etching, but during this etching, the BPSG film 19 was removed (oxide film 22a).
２２ｂよりＢＰＳＧ膜１９膜剤９速くエツチングされる
）、エツチングの制御性が悪＜ＢＰＳＧ膜１９膜剤９化
が難しい欠点がある。(The BPSG film 19 is etched faster than the BPSG film 22b), and has the disadvantage that the etching controllability is poor and it is difficult to form the BPSG film 19 into a film material 9.
（発明が解決しようとする問題点）
上述したように、従来の製造方法では、コンタクトホー
ル内に形成したシリコン層のエツチング保護膜を制御性
良く除去することが困難であり、層間絶縁膜の平坦化も
難しい欠点がある。(Problems to be Solved by the Invention) As described above, in the conventional manufacturing method, it is difficult to remove the etching protection film of the silicon layer formed in the contact hole with good control, and the flatness of the interlayer insulating film is difficult to remove. There are drawbacks that make it difficult to convert.
従って、この発明の目的とするところは、コンタクトホ
ール内に形成したシリコン層のエツチング保護膜を制御
性良く除去することができ、層間絶縁膜の平坦化が容易
な半導体装置の製造方法を提供することである。Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which an etching protection film of a silicon layer formed in a contact hole can be removed with good control, and an interlayer insulating film can be easily flattened. That's true.
［発明の構成］
（問題点を解決するための手段と作用）すなわち、この
発明においては、上記の目的を達成するために、半導体
基体にＣＭＯＳ構造の素子を形成した後、この半導体基
体上に層間絶縁−を形成し、上記半導体基体上に形成さ
れた一方導電型素子上の層間絶縁膜に配線導出用の第１
のコンタクトホールを形成する。次に、この第１のコン
タクトホール内に選択エピタキシャル成長法により第１
のシリコン層を成長形成し、この第１のシリコン層上お
よび上記層間絶縁膜上にエツチング保護膜としてＳＩＮ
膜あるいはＣＶＤ・ＳｉＯ２膜を形成した後、上記半導
体基体上に形成された他方導電型素子上の層間絶縁膜に
配線導出用の第２のコンタクトホールを形成する。そし
て、この第２のコンタクトホール内に選択エピタキシャ
ル成長法により第２のシリコン層を成長形成し、上記第
１．第２のシリコン層上に配線層を形成するようにして
いる。このような製造工程により、エツチング保護膜を
除去する際、層間絶縁膜はエツチングされないので制御
性が良く、層間絶縁膜の平坦化も容易である。[Structure of the Invention] (Means and Effects for Solving the Problems) That is, in order to achieve the above object, in this invention, after forming a CMOS structure element on a semiconductor substrate, A first layer for leading out wiring is formed on the interlayer insulating film on the one conductivity type element formed on the semiconductor substrate.
Form a contact hole. Next, a first contact hole is formed in this first contact hole by selective epitaxial growth.
A silicon layer of SIN is grown as an etching protection film on this first silicon layer and on the interlayer insulating film.
After forming the film or the CVD/SiO2 film, a second contact hole for leading out the wiring is formed in the interlayer insulating film on the other conductivity type element formed on the semiconductor substrate. Then, a second silicon layer is grown in this second contact hole by a selective epitaxial growth method, and a second silicon layer is grown in the first contact hole. A wiring layer is formed on the second silicon layer. With such a manufacturing process, since the interlayer insulating film is not etched when the etching protection film is removed, controllability is good and the interlayer insulating film can be easily flattened.
〈実施例）
以下、この発明の一実施例について図面を参照して説明
する。第１図（ａ）〜（Ｃ）は、製造工程を順次水して
おり、Ｎチャネル型のＭＯＳＦＥＴとＰチャネル型のＭ
ＯＳ ＦＥＴのソース。<Example> Hereinafter, an example of the present invention will be described with reference to the drawings. Figures 1 (a) to (C) show the manufacturing process sequentially, and show an N-channel type MOSFET and a P-channel type MOSFET.
OS FET source.
ドレイン電極の導出に着目している。すなわち、Ｎ型の
半導体基板（比抵抗４Ω・ｃｍ）２６にＰ型のウェル領
域２７を形成した後、コプラナー法により素子分ｍ用の
フィールド酸化＠ ２８１〜２８３を形成する。次に、
上記半導体基板２６上に薄い酸化膜を介してポリシリコ
ン層を形成し、パターニングを行なってゲート電極２９
．３０を形成する。そして、これらのゲート電極２９．
３０をマスクにしてセルファラインに不純物のイオン注
入を行なうことにより、上記半導体基板２６の表面領域
内にはＰ＋型の不純物拡散層（Ｐチャネル型ＭＯ８ＦＥ
Ｔのソース、ドレイン領域）３１ａ、３１ｂを、上記ウ
ェル領域２７の表面領域内にはＮ＋型の不純物拡散層（
Ｎチャネル型ＭＯ８ＦＥＴのソース、ドレイン領域）
３２ａ 、 ３２ｂをそれぞれ形成する。このようにし
てＰチャネル型およびＮチャネル型のＭＯＳ ＦＥＴ
を形成した半導体基体上に、ＣＶＤ−８ｉＯ２膜３３を
例えば３０００人堆積形成し、コ（Ｆ）ＣＶＤ−８ｉ
０２１１ｉ３３上にＢＰＳＧ膜３４膜島４いはＰＳＧ膜
）を７００ＯＡ堆積形成する。そして、このＢＰＳＧ膜
３４膜島４をＰＯＣＭ３雰囲気中で、例えば９００℃の
温度により６０分間アニールして平坦化する。次に、上
記Ｎチャネル型のＭＯＳ ＦＥＴのソース、ドレイン
領域としてのＮ＋型抵拡散層３２ａ３２ｂ上のＣｖＤ−
８ｉＯ２膜３３ｔ’３ Ｊ： （Ｆ Ｂ Ｐ Ｓ Ｇ
ＩＩ！ｔ！ ３４に−Ｄ ンタクトホール３５ａ、３５
ｂを開孔し、これらのコンタクトホール３５ａ、３５ｂ
内に選択エピタキシャル成長法によりＮ＋型のシリコン
層３６ａ、３６ｂを成長形成する。この選択エピタキシ
ャル成長法の条件は、例えばＨ２ガスが１００ Ｍ／ｍ
ｌｎ 。We are focusing on the derivation of the drain electrode. That is, after forming a P-type well region 27 on an N-type semiconductor substrate (specific resistance: 4 Ω·cm) 26, field oxides 281 to 283 for elements m are formed by a coplanar method. next,
A polysilicon layer is formed on the semiconductor substrate 26 through a thin oxide film, and patterned to form a gate electrode 29.
．． form 30. These gate electrodes 29.
30 as a mask, impurity ions are implanted into the self-line, thereby forming a P+ type impurity diffusion layer (P channel type MO8FE) in the surface region of the semiconductor substrate 26.
T source and drain regions) 31a and 31b, and an N+ type impurity diffusion layer (
Source and drain regions of N-channel MO8FET)
32a and 32b are formed, respectively. In this way, P-channel type and N-channel type MOS FET
For example, 3,000 people deposit a CVD-8iO2 film 33 on the semiconductor substrate formed with CO(F)CVD-8i.
A BPSG film 34 (film island 4 or PSG film) of 700 OA is deposited on the 0211i33. Then, this BPSG film 34 film island 4 is flattened by annealing for 60 minutes at a temperature of, for example, 900° C. in a POCM3 atmosphere. Next, the CvD-
8iO2 film 33t'3 J: (F B P S G
II! T! 34-D contact hole 35a, 35
b, and these contact holes 35a, 35b
N+ type silicon layers 36a and 36b are grown therein by selective epitaxial growth. The conditions for this selective epitaxial growth method are, for example, H2 gas at 100 M/m
ln.
５ｉＨ２Ｃｊ２２ガスが４００ｃｃ／ｍｉｎ 、 ＨＣ
ｌ１ｆｊスが１／／１ｎ 、ＰＨ３ガスが２００ｃｃ／
ｍｉｎの流量で、全圧力を１００ｔｏｒｒとし、反応室
内の温度は９００℃とする。5iH2Cj22 gas 400cc/min, HC
l1fj gas is 1//1n, PH3 gas is 200cc/
The total pressure is 100 torr, and the temperature inside the reaction chamber is 900° C. with a flow rate of min.
次に、（ｂ）図に示すように、上記半導体基体上に例え
ば５００人のＳｔＮ膜３７をエツチング保ｌ！膜として
形成し、このＳｉＮ膜３膜管７って上記ＢＰＳＧＩｆ！
３４および上記シリコン１ｉ３６ａ、３６ｂを保護しつ
つ、Ｐチャネル型のＭＯＳ ＦＥＴのソース、トレイ
ン導出用のコンタクトホール３８ａ。Next, as shown in Figure (b), a StN film 37 of, for example, 500 layers is etched on the semiconductor substrate. This SiN film 3 film tube 7 is formed as a film, and this SiN film 3 film tube 7 is the above-mentioned BPSG If!
34 and a contact hole 38a for leading out the source and train of a P-channel type MOS FET while protecting the silicon 1i36a and 36b.
３８ｂを開孔する。38b is drilled.
次に、（Ｃ）図に示すように、上記コンタクトホール３
８ａ、３８ｂ内に選択エピタキシャル成長法によりＰ＋
型のシリコン層３９ａ、３９ｂを成長形成する。この選
択エピタキシャル成長法の条件は、上記シリコン層３６
ａ、３６ｂの形成時におけるＰＨ３ガスに代えて８２１
−１６ガスを用い、他の条件は同じとする。そして、上
記３ｉＮｇ！Ｊ３７をＨＰＯａを用いてエツチング除去
する。その後、スパッタ法により半導体基体上にアルミ
ニウム層を形成し、このアルミニウム層をパターニング
し一〇−
て配線４０ａ〜４０ｄを形成する。Next, as shown in Figure (C), the contact hole 3 is
8a and 38b by selective epitaxial growth.
Mold silicon layers 39a and 39b are grown. The conditions for this selective epitaxial growth method are as follows:
821 instead of PH3 gas when forming a and 36b
-16 gas is used and other conditions are the same. And the above 3iNg! J37 is removed by etching using HPOa. Thereafter, an aluminum layer is formed on the semiconductor substrate by sputtering, and this aluminum layer is patterned to form interconnections 40a to 40d.
このような製造方法によれば、ＳｉＮ膜３膜管７去する
際にＢＰＳＧ膜３４膜島４チングされることがないので
、エツチングの制御が容易であり、ＢＰＳＧｌ１３４を
平坦化できる。According to such a manufacturing method, since the BPSG film 34 is not etched when removing the SiN film 3 and the film tube 7, etching can be easily controlled and the BPSGl 134 can be planarized.
なお、上記実施例では、シ゛リコン層３６ａ、３６ｂの
エツチング保護膜として３ｉＮＩＩ３７を用いたが、こ
れに代えてＣＶＤ−８ｉＯ２膜を用いても良い。In the above embodiment, 3iNII37 was used as the etching protection film for the silicon layers 36a and 36b, but a CVD-8iO2 film may be used instead.
また、配線４０ａ〜４０ｄと拡散層３１ａ、 ３１ｂ、
３２ａ。In addition, the wirings 40a to 40d and the diffusion layers 31a, 31b,
32a.
３２ｂとを接続する場合について説明したが、配線４０
ａ〜４０ｄと半導体基板２６上に形成された配線層、例
えばゲート電Ｉ！ｉ２９あるいは３０とを接続する場合
にも適応が可能なのはもちろんである。32b, but the wiring 40
a to 40d and wiring layers formed on the semiconductor substrate 26, such as gate electrodes I! Of course, it can also be applied when connecting with i29 or i30.
［発明の効果］
以上説明したようにこの発明によれば、コンタクトホー
ル内に形成したシリコン層のエツチング保護膜を制御性
良く除去することができ、層間絶縁膜の平坦化が容易な
半導体装置の製造方法が得られる。[Effects of the Invention] As explained above, according to the present invention, the etching protection film of the silicon layer formed in the contact hole can be removed with good control, and the interlayer insulating film can be easily flattened in a semiconductor device. A manufacturing method is obtained.
第１図はこの発明の一実施例に係わる半導体装置の製造
方法について説明するための図、第２図は従来の半導体
装置の製造方法について説明するための図である。
２６・・・半導体基板、３３・・・ＣＶＤ−８ｉＯ２膜
、３４・Ｂ Ｐ Ｓ Ｇ膜、３５ａ、 ３５ｂ−’１ｇ
１０）コンタクトホール、３６ａ、３６ｂ・・・第１の
シリコン層、３７・・・ＳｉＮ膜（Ｉツチング保護膜）
、３８ａ 、 ３８ｂ−・・第２のコンタクトホール
、３９ａ、３９ｂ・・・第２のシリコン層、４０ａ〜４
０ｄ・・・配線。FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional method for manufacturing a semiconductor device. 26...Semiconductor substrate, 33...CVD-8iO2 film, 34.BPSG film, 35a, 35b-'1g
10) Contact holes, 36a, 36b...first silicon layer, 37...SiN film (I-cutting protective film)
, 38a, 38b--Second contact hole, 39a, 39b--Second silicon layer, 40a-4
0d...Wiring.
Claims (5)
と、上記半導体基体上に層間絶縁膜を形成する工程と、
上記半導体基体上に形成された一方導電型素子上の層間
絶縁膜に配線導出用の第１のコンタクトホールを形成す
る工程と、この第１のコンタクトホール内に選択エピタ
キシャル成長法により第１のシリコン層を成長形成する
工程と、この第１のシリコン層上および上記層間絶縁膜
上にエッチング保護膜を形成する工程と、上記半導体基
体上に形成された他方導電型素子上の層間絶縁膜に配線
導出用の第２のコンタクトホールを形成する工程と、こ
の第２のコンタクトホール内に選択エピタキシャル成長
法により第２のシリコン層を成長形成する工程と、上記
第１、第２のシリコン層上に配線層を形成する工程とを
具備することを特徴とする半導体装置の製造方法。(1) a step of forming a CMOS structure element on a semiconductor substrate; a step of forming an interlayer insulating film on the semiconductor substrate;
forming a first contact hole for leading out wiring in an interlayer insulating film on one conductivity type element formed on the semiconductor substrate; and forming a first silicon layer in the first contact hole by selective epitaxial growth. a step of forming an etching protection film on the first silicon layer and the interlayer insulating film, and a step of leading out wiring to the interlayer insulating film on the other conductivity type element formed on the semiconductor substrate. a step of forming a second contact hole for the second contact hole, a step of growing a second silicon layer in the second contact hole by a selective epitaxial growth method, and a step of forming a wiring layer on the first and second silicon layers. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor device;
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the etching protection film is made of SiN.
１項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the etching protection film is made of CVD SiO_2.
形成された拡散層上に成長形成されることを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方法。(4) The method of manufacturing a semiconductor device according to claim 1, wherein the first and second silicon layers are grown on a diffusion layer formed in a semiconductor substrate.
形成された配線層上に成長形成されることを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方法。(5) The method of manufacturing a semiconductor device according to claim 1, wherein the first and second silicon layers are grown on a wiring layer formed on a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089410A JPS62245657A (en) | 1986-04-18 | 1986-04-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089410A JPS62245657A (en) | 1986-04-18 | 1986-04-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62245657A true JPS62245657A (en) | 1987-10-26 |
Family
ID=13969874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61089410A Pending JPS62245657A (en) | 1986-04-18 | 1986-04-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62245657A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170466A (en) * | 1988-12-22 | 1990-07-02 | Ricoh Co Ltd | Semiconductor integrated circuit device |
| US5116780A (en) * | 1986-11-19 | 1992-05-26 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device having improved contact resistance characteristics |
| JP2007158258A (en) * | 2005-12-08 | 2007-06-21 | Sony Corp | Semiconductor device manufacturing method |
-
1986
- 1986-04-18 JP JP61089410A patent/JPS62245657A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5116780A (en) * | 1986-11-19 | 1992-05-26 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device having improved contact resistance characteristics |
| JPH02170466A (en) * | 1988-12-22 | 1990-07-02 | Ricoh Co Ltd | Semiconductor integrated circuit device |
| JP2007158258A (en) * | 2005-12-08 | 2007-06-21 | Sony Corp | Semiconductor device manufacturing method |
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