JPH0213460B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices such as bipolar transistors and MIS field effect transistors. A semiconductor region having a predetermined conductivity type is formed in the element formation region from the main surface side, and a conductive layer as an electrode or wiring layer connected to the semiconductor region extends on the main surface of the semiconductor substrate. The present invention is directed to a semiconductor device having a configuration of
The semiconductor region and the conductive layer are reliably positioned in the element formation region for the semiconductor region in a mutually self-aligned manner, and an insulating layer is formed on the outer surface of the conductive layer so that the semiconductor region and the conductive layer are easily aligned. Therefore, it is possible to easily manufacture a semiconductor device using a semiconductor substrate having a small area, and accordingly, it is possible to easily manufacture a semiconductor device with excellent performance. This paper aims to propose a new manufacturing method for semiconductor devices.

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

1A to 1V show a first embodiment of a method for manufacturing a semiconductor device according to the present invention, which includes the following sequential steps.

That is, it is obtained in advance. A semiconductor wafer 11 made of P-type silicon as shown in FIG. 1A.
As shown in FIG. 1B, an N+ type semiconductor region 13 is formed from the main surface 12 side by a well-known diffusion method of, for example, an N ^type impurity within the semiconductor region, and then a semiconductor region 13 is formed. On the main surface 12 of the wafer 11, as shown in FIG ^. A semiconductor substrate 15 having a structure in which an N-type semiconductor layer 14 is formed on the main surface 12 of a P-type semiconductor wafer 11 forming a type semiconductor region 13 is obtained.

Next, the semiconductor substrate 15 obtained in this way
As shown in FIG. After forming the oxidation-resistant etching masks 17 and 18, the semiconductor layer 14 is etched using the oxidation-resistant etching masks 17 and 18 as masks, as shown in FIG. 1E. A groove 19 extending from the main surface 16 side is formed in a region of the layer 14 other than under the masks 17 and 18, and then the semiconductor layer 1
When viewed from the main surface 16 side, the semiconductor region 13 is located in the region where the groove 19 of No. 4 is formed.
By ion implantation, an impurity such as boron, which gives a P type, is introduced into the semiconductor layer 14 so as to surround the semiconductor layer 14. Figure 1 F
As shown in FIG.
Insulating regions 20 and 21 (where the semiconductor layer 14 is silicon In this case, a layer of silicon dioxide) is formed in the region below the insulating region 21 to a depth reaching the semiconductor wafer 11 from the insulating region 21 side, surrounding the semiconductor region 13 when viewed from the main surface 16 side. A P-type semiconductor region 22 extending as shown in FIG. Form.

Next, as shown in FIG. 1G, the masks 17 and 18 are removed from above the semiconductor layer 14, that is, the element formation region 23, and then, as shown in FIG. , and an ion implantation mask 25 made of aluminum, for example, which extends over the element formation region 23 but has a window 24 that allows one of the parts of the element formation region 23 sandwiching the insulating region 20 to be exposed to the outside. The element formation region 23 is formed by a method known per se, and then ion implantation treatment of an impurity such as phosphorus that gives N type is performed on the element formation region 23 using a mask 25, and then heat treatment is performed. (The temperature is 1100 ~
1150° C.), and as shown in FIG. Through the heat treatment in the step of forming 20 and 21, the N type impurity contained in the element forming region 23 is diffused from the semiconductor region 13 side, and is connected to the N ⁺ type semiconductor region 26 formed. The N ⁺ type semiconductor region 27 is made of

Next, as shown in FIG. 1J, after removing the mask 25, ion implantation of an impurity such as boron is performed to give a P type from the main surface 16 side, and then heat treatment is performed. Accordingly, as shown in FIG. 1K, a P-type semiconductor extending from the main surface 16 side toward the semiconductor region 26 is formed in the side of the element formation region 23 on which the semiconductor region 26 is not formed. A region 28 is formed. Note that in this case, the semiconductor region 2
P-type impurity ions are also introduced into the region 7 from the main surface 16 side, but since the semiconductor region 27 is N ⁺ type,
No P-type semiconductor region is formed within this semiconductor region 27.

Next, as shown in FIG. 1L, the semiconductor regions 27 and 28 are subjected to thermal oxidation treatment (in the case that the semiconductor regions 27 and 28 are made of silicon, heat treatment in a dry oxygen atmosphere at 900 to 1100° C.), as shown in FIG. 1L. A thin layer is formed on the surface of the semiconductor regions 27 and 28 on the main surface 16 side and is made of an oxide of these materials (silicon dioxide when the semiconductor regions 27 and 28 are made of silicon) and is connected to the insulating regions 20 and 21. Insulating film 2
9 and 30, and then, as shown in FIG. It is formed by a method known per se.

Next, a semiconductor region 2 is formed on the oxidation-resistant layer 31 formed as described above, as shown in FIG.
8 on the adjacent insulating region 21 side, and insulating region 2
An etching mask 33 made of, for example, photoresist and having a window 32 in a region facing the semiconductor region 28 adjacent to that of No. 1 is formed, and then an oxidation-resistant etching mask is formed using this etching mask 33 as a mask. Etching treatment is performed on the protective layer 31 using, for example, CF ₄ gas plasma, and then, for example, using a buffered solution (HF:NH ₄ F:H ₂ O=1:3.5:6.5) on the insulating region 21 and the insulating film 30. By performing the etching process, as shown in FIG. A window 36 that exposes the semiconductor region 28 to the outside is formed in the insulating film 30 through the window 34 of the mask 35 and the window 32 of the etching mask 33, and a window 36 is formed in the insulating region 21 through the windows 34 and 32 of the masks 35 and 33. A groove 37 facing the outside is formed.

Next, as shown in FIG. 1P, a conductive layer 38 containing a P-type impurity, which can be oxidized, and is made of polycrystalline silicon, for example, extends over the etching mask 33, and an insulating film of the semiconductor region 28 is formed. 30
The area facing the outside through the window 36 of the oxidation-resistant mask 35 and the window 32 of the etching mask 33, and the area facing outside through the window 34 of the mask 35 and the window 32 of the mask 33 of the insulating region 21 are continuous. The extending conductive layer 39, which is identical to the conductive layer 38, is formed by low-temperature thin film formation methods known per se, such as sputtering, vapor deposition, etc., without damaging the etching mask 33.

Next, the oxidation-resistant mask 33 is removed using the etching mask 33 using its eluent (if the mask 33 is made of photoresist, a photoresist stripper).
5, thereby removing conductive layer 38 while leaving conductive layer 39, as shown in FIG. 1Q.

Next, as shown in FIG. On the outer surface, the conductive layer 3
An insulating layer 4 made of an oxide of material No. 9 (silicon dioxide when the conductive layer 39 is made of polycrystalline silicon)
0 to be thicker than the insulating films 29 and 30, and introduce P-type impurities contained in the conductive layer 39 into the region below the conductive layer 39 of the semiconductor region 28. The resulting P ⁺
A mold semiconductor region 41 is formed.

Next, for example, for the oxidation-resistant mask 35,
Etching treatment using _CF4 gas plasma,
The first etching process is then performed on the insulating films 29 and 30 using, for example, a buffer solution.
As shown in FIG. S, the oxidation-resistant mask 35 and insulating films 29 and 30 are removed, and
8 and the insulating regions 20 and 21 are exposed to the outside. In this case, insulating layer 40 on the outer surface of conductive layer 39 is etched at the same time as insulating films 29 and 30, but since it is thicker than insulating films 29 and 30, insulating layer 40 is etched as a conductive layer. 39 may be left on the outer surface of the 39.

Next, a conductive layer containing an impurity of, for example, phosphorus and made of, for example, polycrystalline silicon, which gives N type, is formed.
For example, by vapor phase growth, the semiconductor regions 27 and 28, the insulating regions 20 and 21, and the insulating layer 40 are connected and extended, and then the conductive layer is selectively etched. and heat treatment (800 to 1000℃ if the conductive layer is made of polycrystalline silicon and the impurity contained in it is phosphorus).
As shown in FIG. A semiconductor region 42 is formed. Next, from the above-mentioned conductive layer, the insulating regions 20 and 21 and the insulating layer 40 are applied on the semiconductor region 42 and
a conductive layer 43 extending over and around the semiconductor region 42 of the insulating regions 20 and 21; A sexual layer 44 is formed.

Next, as shown in FIG. 1U, windows 45 and 45 continuously extend over the insulating regions 20 and 21, the insulating layer 40, and the conductive layers 43 and 44, and expose the conductive layers 43 and 44 to the outside. 46, and
An insulating layer 48 having a window 47 at a position facing the conductive layer 39 is formed by a method known per se, and a conductive layer 39 is formed below the window 47 of the insulating layer 48 of the insulating layer 40. A window 49 facing the outside is formed.

Next, as shown in FIG. a conductive layer 52 connected to conductive layer 39 through windows 47 and 49 in layers 48 and 40 and extending over insulating layer 48;
It is formed by a method known per se.

The above describes the first method of manufacturing a semiconductor device according to the present invention.
An example of this has been revealed.

The semiconductor device shown in FIG. 1V obtained by this first embodiment has an element formation region 23 separated and defined by an insulating region 21 formed from the main surface side of the semiconductor substrate 15. The region sandwiched between the semiconductor regions 26 and 28 in the element forming region 23 is defined as a collector region, and the semiconductor region 13
and 26 are used as collector compensation and extraction regions, the semiconductor region 27 is used as a collector extraction region, the conductive layer 44 is used as a collector electrode, the conductive layer 51 is used as a collector wiring, the semiconductor region 28 is used as a base region,
The semiconductor region 41 is used as a base extraction region, the conductive layer 39 is used as a base electrode, the conductive layer 52 is used as a base wiring, the semiconductor region 42 is used as an emitter region,
The conductive layer 43 is used as an emitter electrode, and the conductive layer 50
It constitutes an NPN type bipolar transistor with emitter wiring.

Therefore, the first embodiment of the method for manufacturing a semiconductor device according to the present invention shown in FIG. 1 can be said to be an example of the method for manufacturing an NPN type bipolar transistor.

According to the first embodiment of the method for manufacturing a semiconductor device according to the present invention, an insulating region 21 is formed in a semiconductor substrate 15 so as to separate and define an element formation region 23 from the main surface 16 side of the semiconductor substrate 15. (FIG. 1G) and a step (FIG. 1M) of forming an oxidation-resistant layer 31 on the main surface 16 of the semiconductor substrate 15.
Step of forming an etching mask 33 having a window 32 formed at a position facing the (FIG. 1N)
Then, by etching the oxidation-resistant layer 31 using the etching mask 33 as a mask,
a step of forming an oxidation-resistant mask 35 having a window 34 that exposes the element formation region 23 to the outside through the window 32 of the etching mask 33 (O in FIG. 1);
In the element formation region 23, the etching mask 3
A conductive layer 38 that extends onto the etching mask 33 from a region facing outside through the window 32 of No. 3 and the window 34 of the oxidation-resistant mask 35, contains an impurity that provides a predetermined conductivity type, and is oxidizable. 39 (FIG. 1P); and removing the conductive layer 38 extending above the etching mask 33 by removing the etching mask 33 (FIG. 1Q). By thermal oxidation treatment of the conductive layer 39 left on the region facing the outside of the element formation region 23, an insulating layer 40 is formed on the outer surface of the conductive layer 39, and the conductivity of the element formation region 23 is In the region below the conductive layer 39, the conductive layer 39
In the process of forming the first semiconductor region 41 by introducing impurities contained in the first semiconductor region 41 (FIG. 1R) and by removing the oxidation-resistant mask 35, the element formation region 23 is etched. mask 33
Step (first step) of exposing the area facing the outside through the window 32 of the
S) and the step of forming the second semiconductor region 42 by introducing into the element formation region 23 an impurity that gives a conductivity type opposite to the predetermined conductivity type from the externally exposed region (the first Figure T) is used to manufacture a target semiconductor device (in this case, a bipolar transistor).

Therefore, the semiconductor region 41 formed in the element formation region 23 (in this case, as a base extraction region) and the conductive layer 39 connected thereto (in this case, as a base electrode) are mutually connected. In a self-aligned manner, the element formation region 2 is defined by separating the semiconductor region 41 by the insulating region 21.
3, and conductive layer 39.
Accordingly, it forms an insulating layer 40 on the outer surface and can be easily formed.

Therefore, a target semiconductor device can be easily manufactured using the semiconductor substrate 15 having a small area, and accordingly, a semiconductor device with excellent performance can be easily manufactured.

Furthermore, in the case of the first embodiment of the method for manufacturing a semiconductor device according to the present invention shown in FIG. the conductive layer 39 as a base electrode, the semiconductor region 42 as an emitter region, the window for connecting the conductive layer 43 as an emitter electrode thereto, the conductive layer as an emitter electrode 43, the insulating film 40 separating the conductive layers 39 and 43 as a base electrode and an emitter electrode, and the windows for connecting them to the semiconductor regions 41 and 42 as a base extraction region and an emitter region, respectively, is self-contained. Consistently,
Can be accurately positioned and formed.

Further, the conductive layers 39 and 43 as a base electrode and an emitter electrode are connected to the semiconductor regions 41 and 4 as a base extraction region and an emitter region, respectively.
The interval between the windows for connection to the base electrode 2 can be made into a minute interval determined by the insulating layer 40 formed by thermal oxidation on the surface of the conductive layer 39 serving as the base electrode.

Furthermore, for this purpose, the semiconductor region 41 as the base extraction region and the semiconductor region 42 as the emitter region can be brought close to each other in a manner that they are connected as shown in the figure.

Therefore, the desired bipolar transistor can be easily formed on the semiconductor substrate 15 in a small area and with high precision.

Further, for the above-mentioned reason, the area of the semiconductor region 28 serving as the base region can be reduced, so that the PN junction capacitance between the collector bases can be reduced.

Furthermore, a semiconductor region 41 as a base extraction region, and a semiconductor region 42 as an emitter region.
As described above, the base resistance can be made sufficiently low, and a bipolar transistor that operates at high speed can be easily manufactured.

Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 2A to 2I.

In this example, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The method of manufacturing a semiconductor device according to the present invention shown in FIG. 2 includes the following sequential steps.

That is, as shown in FIG. 2A, FIG.
After going through the same steps as described above in FIG.

Next, as shown in FIG. 2B, without removing the masks 17 and 18, an N ⁺ type semiconductor similar to that described above in FIG. A region 27 is formed by implanting N-type impurity ions and subsequent heat treatment, and then, as shown in FIG. A P-type semiconductor region 28 similar to that described above is formed by ion implantation of P-type impurities followed by heat treatment. Note that through the steps described above, the element formation region 23
An N ⁺ type semiconductor region 26 similar to that described above in FIG. 1I is formed therein. Next, as shown in FIG. 2D, a window 32 similar to that described above in FIG.
An etching mask 33 having a
0 and 21 and extending over the masks 17 and 18.

Next, as shown in FIG. 2E, an oxidation-resistant mask 35 having windows 34 similar to those described above in FIG. 1O is formed from the mask 18 by etching the mask 18 using the mask 33 as a mask. Form.

Next, as shown in FIG. 2F, a conductive layer 38 similar to that described above in FIG. A conductive layer 39 similar to that described above in FIG. 1P is formed extending over the areas facing 32 and 34.

Next, as described above in FIG. 1Q, the mask 3
3 leaves conductive layer 39 but removes conductive layer 38, as shown in FIG. 2G.

Next, a conductive layer 3 similar to that described above in FIG.
9, a conductive layer 3 similar to that described above in FIG. 1R is formed, as shown in FIG. 2H.
forming an insulating layer 40 on the outer surface of 9;
A P ⁺ type semiconductor region 41 within the semiconductor region 28 is formed.

Next, as described above in FIG. 1S, the mask 3
5 along with the mask 17, thus obtaining a configuration similar to that described above in FIG. 1S, as shown in FIG. 2I.

Next, although illustration and explanation are omitted, conductive layers 43 and 44 similar to those described above in FIG. 1T are formed, and then windows 45, 46 and 47 similar to those described above in FIG. 1U are formed. an insulating layer 48 and a window 4 of the insulating layer 40 having
9 and then conductive layers 50, 51 and 52 similar to those described above in FIG. 1V.

The second embodiment of the semiconductor device according to the present invention has been clarified above.

Since the semiconductor device manufactured according to the second embodiment has the same configuration as described above in FIG. 1, it is clear that it constitutes an NPN type bipolar transistor. be.

Therefore, the second embodiment of the method for manufacturing a semiconductor device according to the present invention shown in FIG. 2 can also be said to be an example of the method for manufacturing an NPN type bipolar transistor.

Further, according to the second embodiment of the method for manufacturing a semiconductor device according to the present invention shown in FIG. 2, it is similar to the first embodiment of the method for manufacturing a semiconductor device according to the present invention described above with reference to FIG. Although a detailed explanation will be omitted since it is clear that the steps are as follows, this embodiment has the same excellent features as the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3A to 3N.

The method for manufacturing a semiconductor device according to the present invention shown in FIG. 3 includes the following sequential steps.

That is, as shown in FIG. 3B, an oxidation-resistant etching film made of silicon nitride, for example, is deposited on the main surface 62 of a semiconductor substrate 61 made of N-type silicon as shown in FIG. Forming a mask 63, and then using the mask 63 as a mask,
As shown in FIG. 3C, by etching the semiconductor substrate 61, a groove 64 is formed in a region of the semiconductor substrate 61 other than under the mask 63, and then
By thermally oxidizing the semiconductor substrate 61 using the mask 63 as a mask, an insulating region 66 is formed so as to separate and define an element formation region 65 of the semiconductor substrate 61, as shown in FIG. 3D.

Next, as shown in FIG. 3E, after removing the mask 63, the element forming region 65 is subjected to thermal oxidation treatment, as shown in FIG. 3F. An insulating region 6 made of oxide
6, and then, as shown in FIG. Form.

Next, the oxidation-resistant layer 6 formed in this way
8, as shown in FIG.
An etching mask 71 having windows 69 and 70 is formed on opposite sides of the insulating region 66 adjacent to that of No. 5 and on opposite sides of the element forming region 65 adjacent to that of the insulating region 66, respectively. By etching the oxidation-resistant layer 68 using this mask 71 as a mask, and then etching the insulating layer 67, as shown in FIG. 70
An oxidation-resistant mask 74 having windows 72 and 73 thereunder is formed, and an element formation region 65 is formed in the insulating layer 67 through the windows 72 and 73 of the mask 74.
Windows 94 and 95 are formed in the insulating region 66 to expose the outside, and windows 72 and 7 of the mask 74 are formed in the insulation region 66.
The grooves facing outward through 3 form 76 and 77.

Next, as shown in FIG. 3J, a conductive layer 7 containing P-type impurities extending over the mask 71, which can be oxidized, and is made of polycrystalline silicon, for example.
8 and a window 9 in the element formation region 65 and insulating region 66
a conductive layer 79 identical to conductive layer 78 extending over the area facing outward through 4, 72 and 69;
Windows 95 and 7 in the element formation region 65 and insulating region 66
A conductive layer 80, which is the same as conductive layers 78 and 79, is formed extending over the area facing outward through 3 and 70.

Mask 71 is then removed, leaving conductive layers 79 and 80, but removing conductive layer 78, as shown in FIG. 3K.

Next, as shown in FIG. 3L, the conductive layers 79 and 80 are thermally oxidized.
An insulating layer 8 made of an oxide of the material of the conductive layers 79 and 80 is formed on the outer surface including the side surfaces of the conductive layers 79 and 80.
1 and 82, and the element formation region 6.
A P-type semiconductor region 8 is formed in a region under the conductive layers 79 and 80 of No. 5 by introducing P-type impurities contained in the conductive layers 79 and 80.
3 and 84 are formed.

Next, as shown in FIG. 3M, the oxidation-resistant mask 74 is removed by etching the oxidation-resistant mask 74, and then, as shown in FIG. , forming a conductive layer 85 extending over the insulating layers 81 and 82 .

The above concludes the third method of manufacturing a semiconductor device according to the present invention.
An example of this has been revealed.

According to the third embodiment of the method for manufacturing a semiconductor device according to the present invention, an insulating region 66 is formed in a semiconductor substrate 61 so as to separate and define an element formation region 65 from the main surface 62 side. (FIG. 3D) and a step (FIG. 3F and Figure G)
and a step of forming an etching mask 71 on the oxidation-resistant layer 68, in which windows 69 and 70 are formed at least in positions facing the element forming region 65 (FIG. 3H); An oxidation-resistant mask 74 having windows 72 and 73 that exposes the element formation region 65 to the outside through windows 69 and 70 of the etching mask 71 by etching the oxidation-resistant layer 68 using the mask 71 as a mask.
(FIG. 3 I) and the step of forming the element forming region 6
5, it extends from above the region facing outside through the windows 69 and 70 of the etching mask 71 and the windows 72 and 73 of the oxidation-resistant mask 74 to the etching mask 71, and contains impurities that provide a predetermined conductivity type. conductive layer 78 that can be oxidized while
to 80 (FIG. 3J); and a step of removing the conductive layer 78 extending above the etching mask 71 by removing the etching mask 71 (FIG. 3K). The conductive layer 7 is thermally oxidized by thermal oxidation treatment on the conductive layers 79 and 80 left on the region facing the outside of the element formation region 65.
Insulating layers 81 and 82 are formed on the outer surfaces of 9 and 80, and the conductive layer 7 of the element forming region 65 is formed.
forming first semiconductor regions 83 and 84 in the regions below 9 and 80 by introducing impurities contained therein from conductive layers 79 and 80 (FIG. 3L); By removing the mask 74, the windows 69 and 70 of the etching mask 71 and the oxidation-resistant mask 74 in the element formation region 65 are removed.
A step of exposing the thin insulating layer 67 to the outside in a region other than the region facing the outside through the windows 72 and 73 (FIG. 3M), and forming an electrode 85 on the thin insulating film 67 exposed to the outside. process (Fig. 3N), and the target semiconductor device (in this case
The semiconductor device shown in FIG. In addition, the semiconductor regions 83 and 84 are used as a source region and a drain region, respectively, and the semiconductor region 83 in the element formation region 65 is
and 84 is a channel region, the insulating layer 67 is a gate insulating film, and the conductive layers 79, 80, and 85 are respectively used as a source electrode or wiring layer, a drain electrode or wiring layer, and a gate electrode or wiring layer. It constitutes a channel type MIS field effect transistor.

Therefore, the third embodiment of the method for manufacturing a semiconductor device according to the present invention shown in FIG.
This can be said to be an example of a method for manufacturing a field effect transistor.

According to the third embodiment of the method for manufacturing a semiconductor device according to the present invention, although detailed explanation will be omitted, the process is similar to the first embodiment of the method for manufacturing a semiconductor device according to the present invention. Therefore, as in the case of the first embodiment of the semiconductor device manufacturing method according to the present invention, the target semiconductor device can be easily manufactured using the semiconductor substrate 61 having a small area, and the performance can be improved accordingly. An excellent semiconductor device can be easily manufactured.

In addition, in the case of the third embodiment of the method for manufacturing a semiconductor device according to the present invention shown in FIG. windows 9 for connecting conductive layers 79 and 80 as source and drain electrodes to
4 and 95, conductive layers 79 and 80 as a source electrode and a drain electrode, an insulating layer 67 as a gate insulating film, conductive layers 79 and 80 as a source electrode and a drain electrode, respectively, and a conductive layer as a gate electrode. Insulating layers 81 and 82 separating from 85, conductive layer 85 as a gate electrode
can be precisely positioned and formed in a self-aligned manner.

In addition, since the distance between each of the conductive layers 79 and 80 and the conductive layer 85 can be set to a minute distance determined by the insulating layers 81 and 82, the target MIS field effect transistor can be made small. It can be easily constructed on the semiconductor substrate 61 with a high precision and an area as follows.

In addition, in the above description, only a few embodiments of the present invention have been shown. For example, in the first embodiment of the present invention described above in FIG. 1, the oxidation-resistant mask 35 described above in FIG. window 34 and insulating film 3
In the process of obtaining the window 36 of 0, the window 34 of the mask 35 and the window 36 of the insulating film 30 are made larger than the window 32 of the etching mask 33 and extended below the mask 33, as shown in FIG. 4A. Accordingly, in the step of forming the insulating layer 40 on the outer surface of the conductive layer 39 described above in FIG. 1R, the semiconductor region is formed as shown in FIG. 4B. forming an insulating layer 40' extending from insulating layer 40 in a manner forming within 28;
In the process of manufacturing the target semiconductor device described above with reference to FIG. 1V, as shown in FIG. It can also be configured.

In addition, without departing from the spirit of the invention,
It will be obvious that various modifications and changes may be made.

[Brief explanation of drawings]

FIGS. 1A to 1V are schematic cross-sectional views showing sequential steps of a first embodiment of the method for manufacturing a semiconductor device according to the present invention. 2A to 2I are schematic cross-sectional views showing sequential steps of a second embodiment of the method for manufacturing a semiconductor device according to the present invention. Figure 3 A-N
2A and 2B are schematic cross-sectional views showing sequential steps of a third embodiment of the method for manufacturing a semiconductor device according to the present invention. 4A to 4C are schematic cross-sectional views showing successive steps of another embodiment of the method for manufacturing a semiconductor device according to the present invention. 11...Semiconductor wafer, 1
2, 16, 62...main surface, 13, 14, 22, 2
6, 27, 28, 41, 42, 83, 84... semiconductor region, 15, 61... semiconductor substrate, 17, 1
8, 25, 33, 35, 63, 71, 74...mask, 19, 37, 64, 76, 77... groove, 2
0, 21, 66... Insulating region, 23, 65... Element formation region, 24, 32, 34, 36, 45, 4
6, 47, 49, 69, 70, 72, 73, 9
4,95...Window, 29,30...Insulating film, 31,
68... Oxidation-resistant layer, 38, 39, 43, 44,
50, 51, 52, 78, 79, 80, 85...
Conductive layer, 40, 48, 67, 81, 82...Insulating layer.

Claims (1)

[Claims] 1. A step of forming an insulating region in a semiconductor substrate so as to separate and define an element formation region from the main surface side of the semiconductor substrate, and forming an oxidation-resistant layer on the main surface of the semiconductor substrate. forming an etching mask on the oxidation-resistant layer, the etching mask having a window formed at least at a position facing the element formation region; using the etching mask as a mask, forming an oxidation-resistant mask having a window that allows the element formation region to be exposed to the outside through the window of the etching mask by etching the oxidation-resistant layer; forming a conductive layer that extends onto the etching mask from a region facing outside through the window of the mask and the window of the oxidation-resistant mask, contains an impurity that provides a predetermined conductivity type, and is oxidizable; a step of removing the conductive layer extending above the etching mask by removing the etching mask; and a step of removing the conductive layer extending above the etching mask; By thermal oxidation treatment of the layer, an insulating layer is formed on the outer surface of the conductive layer, and an insulating layer is formed in the region under the conductive layer in the element formation region. A step of forming a first semiconductor region by introducing an impurity, and removing the oxidation-resistant mask allows the etching mask to pass through the etching mask window and the oxidation-resistant mask window in the element formation region. A step of exposing a region other than the region facing the outside to the outside, and introducing an impurity giving a conductivity type opposite to the predetermined conductivity type from the exposed region into the element forming region. 2. A method for manufacturing a semiconductor device, comprising the step of forming a second semiconductor region. 2 forming an insulating region in a semiconductor substrate so as to separate and define an element formation region from the main surface side; forming a thin insulating film on the main surface of the semiconductor substrate; a step of forming an oxidation-resistant layer; a step of forming an etching mask having a window formed on the oxidation-resistant layer at least at a position facing the element formation region; forming an oxidation-resistant mask having a window that allows the element formation region to be exposed to the outside through the window of the etching mask by etching the oxidation-resistant layer using the etching mask; The region extends from above the region facing the outside through the window of the etching mask and the window of the oxidation-resistant mask, extends above the etching mask, contains impurities that give a predetermined conductivity type, and can be oxidized. a step of forming a conductive layer; a step of removing the conductive layer extending above the etching mask by removing the etching mask; and a region of the element formation region facing the outside. By thermal oxidation treatment of the conductive layer left above, an insulating layer is formed on the outer surface of the conductive layer, and the conductive layer is formed in the region under the conductive layer in the element formation region. forming a first semiconductor region by introducing impurities contained therein; and removing the oxidation-resistant mask to remove the etching mask window and the etching mask from the element formation region. The method includes the steps of: exposing the thin insulating film to the outside in a region other than the region facing the outside through the window of the oxidation-resistant mask; and forming an electrode on the thin insulating film exposed to the outside. Characteristic manufacturing method for semiconductor devices.