JPH0212029B2 - - Google Patents
Info
- Publication number
- JPH0212029B2 JPH0212029B2 JP56089240A JP8924081A JPH0212029B2 JP H0212029 B2 JPH0212029 B2 JP H0212029B2 JP 56089240 A JP56089240 A JP 56089240A JP 8924081 A JP8924081 A JP 8924081A JP H0212029 B2 JPH0212029 B2 JP H0212029B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- region
- electrode
- source
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 23
- 239000005360 phosphosilicate glass Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000005368 silicate glass Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に相
補型MIS FETの電極形成工程の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in the electrode formation process of a complementary MIS FET.
相補型MIS FET例えばシリコン基板表面にｎ
チヤネル及びｐチヤネルMOS FETの双方を具
備せしめたＣ MOS FETを高密度化、高集積
化することを目的として、基板表面を被覆する絶
縁膜及び燐硅酸ガラス（PSG）層を、リアクテ
イブ・イオン・エツチング法のようなドライエツ
チング法により選択的に除去してソース及びドレ
イン電極窓を開口することにより、位置合せ余裕
を微小化する製造方法が既に提唱されている。 Complementary MIS FET For example, n
In order to increase the density and integration of CMOS FETs, which are equipped with both channel and p-channel MOS FETs, the insulating film and phosphosilicate glass (PSG) layer covering the substrate surface are coated with reactive ions. - A manufacturing method has already been proposed in which the alignment margin is made smaller by selectively removing the material using a dry etching method such as an etching method to open source and drain electrode windows.
上記製造方法は、リアクテイブ・イオン・エツ
チング法のような直進性を有するドライエツチン
グ法を用いてソース及びドレインの電極窓を開口
することにより電極窓内壁面を基板表面に対し略
垂直な壁面となし得ることから、従来の湿式エツ
チング法を用いて開口した場合に電極窓の内壁面
がテーパ面となるために生じるゲート電極肩部を
被覆するPSG層が極度に薄くなるという危険性
が除去されるのを利用し、従来設けられていたゲ
ート電極とソース及びドレイン電極窓との間隔の
余裕を大幅に削減し、素子の微細化を行なおうと
するものである。 In the above manufacturing method, the inner wall surface of the electrode window is made almost perpendicular to the substrate surface by opening the source and drain electrode windows using a linear dry etching method such as reactive ion etching method. This eliminates the risk of the PSG layer covering the gate electrode shoulder becoming extremely thin due to the tapered inner wall surface of the electrode window when opened using the conventional wet etching method. By utilizing this, the conventionally provided spacing margin between the gate electrode and the source and drain electrode windows is significantly reduced, thereby attempting to miniaturize the device.
上記製造方法ではゲート電極肩部のPSG層が
薄くなる危険は除去し得るが、その反面電極窓の
位置が僅かにずれた場合にｎチヤネルMOS
FETのｎ型ソース領域或いはドレイン領域とｐ
型の素子形成領域とが電極により短絡することが
ある。 The above manufacturing method can eliminate the risk of thinning of the PSG layer at the shoulder of the gate electrode, but on the other hand, if the position of the electrode window is slightly shifted, the n-channel MOS
FET's n-type source or drain region and p-type
There may be a short circuit between the mold and the element forming area due to the electrode.
本発明の目的は上述の派生的問題点を除去し、
ｎ型のソース或いはドレイン領域とｐ型の素子形
成領域とが電極により短絡する恐れのない半導体
装置の製造方法を提供することにある。 The purpose of the present invention is to eliminate the above-mentioned derivative problems,
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which there is no possibility that an n-type source or drain region and a p-type element formation region are short-circuited by an electrode.
本発明の特徴は同一半導体基板上にｎチヤネル
及びｐチヤネルMOS FET素子を具備する半導
体装置を製造するに当り、前記ｎチヤネル及びｐ
チヤネルMOS FET素子双方のゲート電極表面
を含む半導体基板上に第１の絶縁膜とその上に燐
硅酸ガラス層を形成し、該燐硅酸ガラス層及び第
１の絶縁膜により選択的に除去してソース及びド
レイン電極窓を開口し、該電極窓部において露出
せる半導体基板表面に第２の絶縁膜を形成したの
ち、前記ｎチヤネル素子領域表面に形成された前
記第２の絶縁膜を除去する工程と、前記燐硅酸ガ
ラス層を加熱溶融せしめる工程と、前記残留せる
第２の絶縁膜を除去して前記電極窓部において半
導体基板表面を露出せしめる工程と、該電極窓部
において露出せる半導体基板表面とオーミツク接
触するソース及びドレイン電極を形成する工程と
を含むことにある。 A feature of the present invention is that when manufacturing a semiconductor device including n-channel and p-channel MOS FET elements on the same semiconductor substrate, the n-channel and p-channel MOS FET elements are
A first insulating film and a phosphosilicate glass layer are formed on the semiconductor substrate including the gate electrode surfaces of both channel MOS FET elements, and selectively removed by the phosphosilicate glass layer and the first insulating film. After opening source and drain electrode windows and forming a second insulating film on the surface of the semiconductor substrate exposed in the electrode windows, removing the second insulating film formed on the surface of the n-channel element region. a step of heating and melting the phosphosilicate glass layer; a step of removing the remaining second insulating film to expose the surface of the semiconductor substrate at the electrode window; and forming source and drain electrodes in ohmic contact with the surface of the semiconductor substrate.
以下本発明の一実施例を第１図〜第５図の要部
断面図を用いて製造工程の順に説明する。 An embodiment of the present invention will be described below in the order of manufacturing steps using sectional views of main parts shown in FIGS. 1 to 5.
本実施例においては、ｎ型領域１と表面の所定
区域に形成されたｐ型の島状領域（ｐウエル）２
とからなるシリコン基板３を用い、前記ｐウエル
２内にｎチヤネルMOS FET素子とｎ型シリコ
ン基板１表面にｐチヤネルMOS FET素子を形
成する例を掲げて説明する。 In this embodiment, an n-type region 1 and a p-type island region (p well) 2 formed in a predetermined area on the surface are used.
An example will be described in which an n-channel MOS FET element is formed in the p-well 2 and a p-channel MOS FET element is formed on the surface of the n-type silicon substrate 1 using a silicon substrate 3 consisting of the following.
第１図において、４は素子間絶縁分離領域で例
えば選択酸化法により形成したフイールド酸化
膜、５，６はｎ型のソース及びドレイン領域、
７，８はｐ型のソース及びドレイン領域、９，
９′はゲート酸化膜、１０，１０′は例えばシリコ
ン多結晶よりなるゲート電極である。 In FIG. 1, reference numeral 4 denotes an inter-element insulation isolation region, which is a field oxide film formed by, for example, a selective oxidation method; 5 and 6 denote n-type source and drain regions;
7, 8 are p-type source and drain regions; 9,
9' is a gate oxide film, and 10 and 10' are gate electrodes made of polycrystalline silicon, for example.
上記シリコン基板３に加熱酸化処理を施こし
て、第２図に見られるようにシリコン基板３表面
の露出せる部分即ちソース及びドレイン領域５，
６，７，８表面と、ゲート電極１０，１０′のシ
リコン多結晶層表面を酸化して、第１の絶縁膜で
ある二酸化シリコン（SiO2）膜１１を形成し、
次いで該SiO2膜１１上に化学気相成長（CVD）
法により燐硅酸ガラス（PSG）層１２を形成す
る。次いでリアクテイブ・イオン・エツチング法
のような直進性を有するドライエツチング法によ
りソース、ドレイン領域５，６，７，８上の
PSG層１２及びSiO2膜１１を選択的に除去して、
電極窓１３，１４，１５，１６を開口する。 The silicon substrate 3 is subjected to a thermal oxidation treatment, and as shown in FIG.
6, 7, 8 surfaces and the silicon polycrystalline layer surfaces of gate electrodes 10, 10' are oxidized to form a silicon dioxide (SiO 2 ) film 11 which is a first insulating film;
Next, chemical vapor deposition (CVD) is performed on the SiO 2 film 11.
A phosphosilicate glass (PSG) layer 12 is formed by a method. Next, the source and drain regions 5, 6, 7, and 8 are etched using a dry etching method that has straightness, such as reactive ion etching.
selectively removing the PSG layer 12 and the SiO 2 film 11;
Electrode windows 13, 14, 15, and 16 are opened.
このとき電極窓パターンの位置が僅かにずれて
いて、電極窓１３〜１６のうちのどれか、例えば
電極窓１４がフイールド酸化膜４の端部と重なり
合つたとする。このような場合にはフイールド酸
化膜４の端部が除去されて、図示のごとくｎ型ド
レイン領域６とｐウエル２の間の接合１７の端部
が露出してしまう。 At this time, it is assumed that the position of the electrode window pattern is slightly shifted and one of the electrode windows 13 to 16, for example, the electrode window 14 overlaps with the end of the field oxide film 4. In such a case, the end of field oxide film 4 is removed, and the end of junction 17 between n-type drain region 6 and p-well 2 is exposed as shown.
このようになると従来の製造方法では上記ｎ型
ドレイン領域６とｐウエル２とはこのあとの工程
で上記電極窓１４に形成される電極によつて短絡
され、素子は不良品とならざるを得ない。そのた
め当初意図した程素子を微細化することができな
かつた。本発明はこの点を後述する製造工程によ
り改善しようとするものである。 In this case, in the conventional manufacturing method, the n-type drain region 6 and the p-well 2 are short-circuited by the electrode formed in the electrode window 14 in a subsequent process, and the device is inevitably defective. do not have. Therefore, it was not possible to miniaturize the element as originally intended. The present invention attempts to improve this point through the manufacturing process described below.
上記工程に引き続き、第３図に見られる如くシ
リコン基板３に加熱酸化処理を施こし電極窓１３
〜１６部基板表面にSiO2膜（第２の絶縁膜）１
８，１９，２０，２１を形成する。ここまでは従
来の製造方法と異なる所はない。 Following the above steps, the silicon substrate 3 is heated and oxidized as shown in FIG.
~16 parts SiO 2 film (second insulating film) 1 on the substrate surface
8, 19, 20, 21 are formed. Up to this point, there is no difference from the conventional manufacturing method.
本実施例においてはこのあと第４図に示すよう
にｐチヤネル素子の表面のSiO2膜１８，１９を
選択的に除去してｎ型ソース及びドレイン領域
５，６表面を露出せしめる。このようにするには
ｎチヤネル素子部をレジスト膜（図示せず）等に
より被覆してSiO2膜のエツチング処理を行なえ
ばよい。次いでシリコン基板３を所定の温度で加
熱処理を行なうことにより、PSG層１２を溶融
せしめ図示の如く肩部をなだらかにする。本工程
においてPSG層１２に含まれるｎ型不純物の燐
（Ｐ）が蒸発し、これが前記電極窓１３，１４部
基板表面に拡散する。そのため前述の電極１４部
において露出せるｐウエル２表面もｎ型に変換さ
れ、図示のようにｎ型のソース領域６と一体化す
る。このように本実施例においてはｎチヤネル素
子の電極窓内のSiO2膜１８，１９を除去してか
らPSG層を溶融せしめることによりｎチヤネル
素子の電極窓部基板表面をすべてｎ型とすること
ができる。この工程でｐチヤネル素子ではSiO2
膜２０，２１に阻止されて蒸発した燐（Ｐ）がｐ
型のソース及びドレイン領域７，８中に拡散する
ことはない。 In this embodiment, as shown in FIG. 4, the SiO 2 films 18 and 19 on the surface of the p-channel device are then selectively removed to expose the surfaces of the n-type source and drain regions 5 and 6. In order to do this, the n-channel element portion may be covered with a resist film (not shown) or the like, and the SiO 2 film may be etched. Next, the silicon substrate 3 is heated at a predetermined temperature to melt the PSG layer 12 and make the shoulder portion smooth as shown in the figure. In this step, phosphorus (P), which is an n-type impurity contained in the PSG layer 12, is evaporated and diffused onto the surface of the substrate at the electrode windows 13 and 14. Therefore, the surface of the p-well 2 exposed at the electrode 14 portion mentioned above is also converted to n-type, and is integrated with the n-type source region 6 as shown. In this way, in this embodiment, by removing the SiO 2 films 18 and 19 within the electrode window of the n-channel device and then melting the PSG layer, the entire surface of the substrate at the electrode window of the n-channel device is made n-type. Can be done. In this process, SiO 2
The evaporated phosphorus (P) blocked by the membranes 20 and 21 is p
It does not diffuse into the source and drain regions 7, 8 of the mold.
次いで第５図に示すようにアルミニウム（Al）
のような導電材料を蒸着法或いはスパツタリング
法等により被着せしめ、これをパターニングし
て、各電極窓１３〜１６においてそれぞれ基板３
表面とオーミツク接触をなすｎチヤネル素子のソ
ース、ドレイン電極２２，２３及びｐチヤネル素
子のソース及びドレイン電極２４，２５を形成し
て、Ｃ MOS FETが完成する。 Next, as shown in Figure 5, aluminum (Al)
A conductive material such as is deposited by a vapor deposition method or a sputtering method, and is patterned to form a conductive material on the substrate 3 in each of the electrode windows 13 to 16.
The CMOS FET is completed by forming the source and drain electrodes 22 and 23 of the n-channel device and the source and drain electrodes 24 and 25 of the p-channel device, which make ohmic contact with the surface.
本実施例によれば上述の電極窓１４部において
も上記電極窓１４内基板表面がすべてｎ型に変換
されるので従来のように短絡不良を生じることは
ない。なお従来の製造方法ではｎチヤネル素子部
もSiO2膜１８，１９を残せしめたままPSG層１
２の加熱溶融工程を行なつていたため、露出せる
ｐ型の表面をｎ型に変換することができなかつた
ものである。 According to this embodiment, even in the electrode window 14 portion, the entire surface of the substrate within the electrode window 14 is converted to n-type, so that short circuit failures do not occur as in the conventional case. In addition, in the conventional manufacturing method, the PSG layer 1 is left on the N-channel element part with the SiO 2 films 18 and 19 remaining.
Since the heating and melting step No. 2 was performed, the exposed p-type surface could not be converted to n-type.
以上説明したごとく本発明によりたとえ電極窓
の位置ずれがあつても素子が不良となることがな
くなるので、素子を十分に微細化することが可能
となり、しかも製造歩留が向上する。 As explained above, according to the present invention, even if the electrode window is misaligned, the element will not become defective, so it becomes possible to sufficiently miniaturize the element, and furthermore, the manufacturing yield is improved.
第１図〜第５図は本発明の一実施例を製造工程
の順に示す要部断面図である。
図において、１はｎ型領域、２はｐ型島状領
域、３は半導体基板、４は素子間絶縁分離領域、
５，６はｎチヤネルMIS FET素子のソース、ド
レイン領域、９はゲート絶縁膜、１０はゲート電
極、１１は第１の絶縁膜、１２は燐硅酸ガラス
層、１３，１４，１５，１６は電極窓、１８，１
９，２０，２１は第２の絶縁膜、２２，２３，２
４，２５は電極を示す。
1 to 5 are sectional views of essential parts showing an embodiment of the present invention in the order of manufacturing steps. In the figure, 1 is an n-type region, 2 is a p-type island region, 3 is a semiconductor substrate, 4 is an inter-element isolation region,
5 and 6 are source and drain regions of the n-channel MIS FET element, 9 is a gate insulating film, 10 is a gate electrode, 11 is a first insulating film, 12 is a phosphosilicate glass layer, 13, 14, 15, and 16 are Electrode window, 18,1
9, 20, 21 are second insulating films, 22, 23, 2
4 and 25 indicate electrodes.
Claims (1)
素子間絶縁分離領域により画定された一導電型及
び逆導電型の素子形成領域と、それぞれの領域表
面にそれぞれの領域とは反対導電型のソース及び
ドレイン領域と該ソース及びドレイン領域に挾ま
れた領域上にゲート絶縁膜を介して配設されたゲ
ート電極とを有するｎチヤネルMIS FET及びｐ
チヤネルMIS FETの双方を具備してなる半導体
装置を製造するに当り、前記ｎチヤネル及びｐチ
ヤネルMIS FET双方のゲート電極表面を含む半
導体基板上に第１の絶縁膜を形成する工程と、該
第１の絶縁膜上に燐硅酸ガラス層を形成する工程
と、該燐硅酸ガラス層及び前記第１の絶縁膜を選
択的に除去して前記双方のソース及びドレイン領
域に対する電極窓を開口する工程と、該電極窓部
において露出せる半導体基板表面に第２の絶縁膜
を形成する工程と、前記ｎチヤネルMIS FET領
域表面に形成された前記第２の絶縁膜を除去する
工程と、前記燐硅酸ガラス層を加熱溶融せしめる
工程と、前記残留せる第２の絶縁膜を除去して前
記電極窓部において半導体基板表面を露出せしめ
る工程と、該電極窓部において露出せる半導体基
板表面とオーミツク接触するソース及びドレイン
電極を形成する工程とを含むことを特徴とする半
導体装置の製造方法。1. An inter-element insulation isolation region on the surface of a semiconductor substrate, element formation regions of one conductivity type and opposite conductivity type defined by the inter-element insulation isolation region, and a source of an opposite conductivity type to each region on the surface of each region. An n-channel MIS FET and a p-channel MIS FET having a drain region and a gate electrode disposed on a region sandwiched between the source and drain regions with a gate insulating film interposed therebetween.
In manufacturing a semiconductor device comprising both a channel MIS FET, a step of forming a first insulating film on a semiconductor substrate including surfaces of gate electrodes of both the n-channel and p-channel MIS FETs; forming a phosphosilicate glass layer on the first insulating film; and selectively removing the phosphosilicate glass layer and the first insulating film to open electrode windows for both source and drain regions. a step of forming a second insulating film on the surface of the semiconductor substrate exposed in the electrode window portion; a step of removing the second insulating film formed on the surface of the n-channel MIS FET region; a step of heating and melting the silicate glass layer; a step of removing the remaining second insulating film to expose the surface of the semiconductor substrate at the electrode window; and ohmic contact with the surface of the semiconductor substrate exposed at the electrode window. 1. A method of manufacturing a semiconductor device, comprising the step of forming source and drain electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56089240A JPS57204161A (en) | 1981-06-09 | 1981-06-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56089240A JPS57204161A (en) | 1981-06-09 | 1981-06-09 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57204161A JPS57204161A (en) | 1982-12-14 |
| JPH0212029B2 true JPH0212029B2 (en) | 1990-03-16 |
Family
ID=13965214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56089240A Granted JPS57204161A (en) | 1981-06-09 | 1981-06-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57204161A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2508782B2 (en) * | 1988-01-27 | 1996-06-19 | 日本電気株式会社 | Method for manufacturing CMOS semiconductor device |
| US5759869A (en) * | 1991-12-31 | 1998-06-02 | Sgs-Thomson Microelectronics, Inc. | Method to imporve metal step coverage by contact reflow |
-
1981
- 1981-06-09 JP JP56089240A patent/JPS57204161A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57204161A (en) | 1982-12-14 |
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