JPS6224342A - Controller incorporating memory data protection circuit - Google Patents

Abstract

PURPOSE:To protect data on a memory from destruction when runaway occurs in a CPU by inhibiting the memory access before an access is given to the released address of a data protecting circuit in a writing mode. CONSTITUTION:A data protecting circuit 6 consists of a latch circuit 10 and a negative AND gate 11. The memory write control signal 12 is usually kept at H and the gate 11 has no actuation. The memory write signal WE' is set under a write unable state. Under such conditions, the pulse is applied to a clear terminal 13 of a latch circuit 10 with the data write release signal. Thus the signal 12 is set at L and the signal WE' is validated. Then an access is given to a memory by a memory access signal and the signal 12 is reset to H. Thus the memory access is inhibited in case said procedure is not carried out. As a result, the memory can be protected against a wrong writing action and the reliability of data is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is mainly applicable to various control devices using a microprocessor as a WA processing device. I! The present invention relates to a control device including a protection circuit for preventing data, etc., from being destroyed when the device goes out of control.

BACKGROUND OF THE INVENTION In recent years, the number of various control devices using microcomputers has increased, and it has become necessary for these devices to have long-term reliability.

FIG. 4 shows an embodiment of a conventional WJ control device. 1 is arithmetic processing 1g! 11 (hereinafter referred to as CPU), which interfaces with program data stored in read-only memory 2 (hereinafter referred to as ROM) or random access memory 3 (hereinafter referred to as RAM) when necessary. 4, it exchanges data with external equipment and performs the desired control.

Problems to be Solved by the Invention In such a conventional configuration, unintended operation or processing (runaway) may occur due to temporary power fluctuations or external noise. Even if an M-run monitoring circuit is adopted in the system, it only prevents the system from going down and is powerless to protect data.

It is an object of the present invention to provide a control device capable of protecting data on a memory from being destroyed in the event of runaway of a CPU.

Means for Solving the Problems A control device with a built-in memory data protection circuit according to the present invention includes: an arithmetic processing device that performs various dance processing according to program data; a protected memory that stores performance data of the performance processing device; The interface that connects the performance processing device and the external circuit is normally in a state where writing to the protected memory is disabled, but when the release address is accessed during a write-in, the protected memory becomes writable, and the data is automatically written immediately after data is written. The present invention is characterized in that a data protection circuit is provided to protect the protected memory data by returning the protected memory to a writable state.

Effect: According to this configuration, it is possible to write into the memory only by accessing the release address of the data protection circuit at the time of writing, and since it is not possible to write to the memory unless this procedure is followed, the data in the memory may be lost due to runaway of the arithmetic processing unit. can be protected.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 3.

FIG. 1 shows a control device with a built-in memory data protection circuit according to the present invention. FIG. 2 is a timing diagram when accessing data on the memory, and FIG. 3 is a specific circuit diagram of the data protection circuit 6 in FIG. 1.

First, the configuration of an embodiment of the present invention will be explained with reference to FIG.

The CPU exchanges programs and data stored in the ROM 2 and the first RAM 3 with external devices through the interface 4 when necessary to perform desired operations and processes. It is stored in the RAM 5 of. Reference numeral 6 denotes a data protection circuit that prevents data in the second RAM 5 to be protected from being destroyed when the CPU 1 goes out of control due to an external factor. In the data protection circuit 6, as shown in FIG. 2, the memory write control signal is normally "H" and polishing is not possible, but the falling pulse 7 of the data write release signal causes the memory write control signal to be disabled. When the control signal becomes "Yes", only one memory access is allowed ("No" period 8), and when reading and writing to the memory is performed with the pulse of the memory access signal C8, the memory is read and written at the rising edge of the pulse 9. The write control signal becomes "H" and writing is disabled.

The specific structure of the data protection circuit 6 is, as shown in FIG. The memory write signal (WE
') are not writable. In this state, the data capture release signal is used to clear the latch circuit 10 at the clear terminal 13.
When a pulse is applied to , the memory write control signal 12 becomes “
"L", and the memory write signal (WE') becomes valid for the memory.After that, when the memory is accessed by the memory access signal, the memory write control signal 1
2 is set to "H", memory access is prohibited unless the above procedure is followed.

As described in the detailed description of the invention, the control device of the present invention normally disables writing to the protected memory, but when the release address is accessed during writing, the control device enables writing to the protected memory, and immediately after data is written. We have installed a data protection circuit that protects the protected memory data by automatically returning the protected memory to a write-disabled state, making it possible to set procedures and restrictions on the operation of writing into the memory that is subject to data protection. It is possible to protect against illegal memory writing and improve data reliability.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the control device of the present invention;
2 is a timing diagram of the data protection circuit shown in FIG. 1, FIG. 3 is a specific circuit diagram of the data protection circuit shown in FIG. 1, and FIG. 4 is a configuration diagram of a conventional control device 11.
1...Dialogue processing device, 2...Read-only
3... First random access memory (RAM), 4... Interface, 5... Second random access memory [protected memory],
6... Data protection circuit, 10... Latch circuit, 11
...Negative logic AND gate agent Yoshihiro Morimoto Figure 1 Figure 2 To CPU 64 Figure 4

Claims (1)

[Claims] 1. An arithmetic processing unit that performs various arithmetic processing according to program data, a protected memory that stores the arithmetic data of this arithmetic processing unit, an interface that connects the arithmetic processing unit to an external circuit, and usually a protected memory. Data that protects the protected memory data by making the protected memory writable when the release address is accessed during writing when the memory is in a writable state, and automatically returning the protected memory to the writable state immediately after data is written. A suppressor with a built-in memory data protection circuit.